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advanced communication devices corp advance information data sheet: ACD82224 ACD82224 24 ports 10/100 fast ethernet switch last update: s ep te mb er 1 9 , 2000 please check acd ? s website for update information before starting a design web site: ht tp://www.acdcorp.com or contact acd at: email: support@acdcorp.com tel: 510-354-6810 fax: 510-354-6834 acd confidential material use under non - disclosure agreement only. no reproduction or redistribution without acd?s prior permission.
page 1 of 77 confidential page 1 1 content list 1. general description ................................ ................................ ................................ ............. 3 2. major features ................................ ................................ ................................ ........................ 5 3. system block diagram ................................ ................................ ................................ ......... 5 4. system description ................................ ................................ ................................ ................ 6 macs, rmii & mii in terfaces ................................ ................................ ................................ ......... 6 queue manager ................................ ................................ ................................ ................................ 6 built - in arl & external - arl interface ................................ ................................ .......................... 6 register & uart interface ................................ ................................ ................................ .............. 7 external - mib & external - mib interface ................................ ................................ .......................... 7 5. functional description ................................ ................................ ................................ ....... 8 frame format ................................ ................................ ................................ ................................ ... 8 start of frame detection ................................ ................................ ................................ ................... 8 frame reception ................................ ................................ ................................ ............................... 8 preamble bit proce ssing ................................ ................................ ................................ ................... 9 destination address processing ................................ ................................ ................................ ........ 9 source address processing ................................ ................................ ................................ ............... 9 frame data ................................ ................................ ................................ ................................ ....... 9 fcs calculation ................................ ................................ ................................ ............................... 9 illega l frame length & extra - long frame ................................ ................................ ...................... 10 frame filtering ................................ ................................ ................................ ............................... 10 jabber lockup protection ................................ ................................ ................................ ................ 10 excessive collision ................................ ................................ ................................ ......................... 10 frame forwarding ................................ ................................ ................................ .......................... 11 frame transmission ................................ ................................ ................................ ....................... 11 shared buffer ................................ ................................ ................................ ................................ . 11 starvation control scheme ................................ ................................ ................................ ............. 12 flow control scheme ................................ ................................ ................................ ..................... 13 port - based vlan support (registers 23 & 24) ................................ ................................ .............. 13 port trunking ................................ ................................ ................................ ................................ . 14 dumping port ................................ ................................ ................................ ................................ . 14 spanning tree support ................................ ................................ ................................ ................... 15 queue management ................................ ................................ ................................ ........................ 15 phy management ................................ ................................ ................................ .......................... 15 phy interface ................................ ................................ ................................ ................................ . 15 sram interface ................................ ................................ ................................ .............................. 16 cpu interface ................................ ................................ ................................ ................................ . 16 arl interface ................................ ................................ ................................ ................................ . 16 mib interface ................................ ................................ ................................ ................................ . 16 led interface ................................ ................................ ................................ ................................ . 16 life pulse ................................ ................................ ................................ ................................ ....... 17 6. interface description ................................ ................................ ................................ ........ 18 rmii interface (rmii) ................................ ................................ ................................ .................... 19 phy management interface ................................ ................................ ................................ ............ 19 cpu interface ................................ ................................ ................................ ................................ . 20 sram interface ................................ ................................ ................................ .............................. 21 arl & mib interfaces ................................ ................................ ................................ ................... 22 led interface ................................ ................................ ................................ ................................ . 23 configuration interface ................................ ................................ ................................ ................... 25 other interface ................................ ................................ ................................ ............................... 26 7. register description ................................ ................................ ................................ ........... 27 intsrc register (register 1) ................................ ................................ ................................ ........... 28
page 2 of 77 confidential page 2 2 syserr register (register 2) ................................ ................................ ................................ .......... 29 par register (register 3) ................................ ................................ ................................ ................. 29 pmerr register (register 4) ................................ ................................ ................................ ........... 29 act register (register 5) ................................ ................................ ................................ ................. 29 sal & sah register (register 8,9) ................................ ................................ ................................ .. 30 uth regis ter (register 10) ................................ ................................ ................................ ............... 30 bth register (register 11) ................................ ................................ ................................ ............... 31 minl & minh register (register 12,13) ................................ ................................ ......................... 31 maxl & maxh register (register 14,15) ................................ ................................ ...................... 31 sys cfg register (register 16) ................................ ................................ ................................ ........ 32 intmsk register (register 17) ................................ ................................ ................................ ........ 33 speed register (register 18) ................................ ................................ ................................ ........... 33 link register (register 19) ................................ ................................ ................................ ............. 33 nfwd regis ter (register 20) ................................ ................................ ................................ ............ 34 nbp register (register 21) ................................ ................................ ................................ ................ 34 nport register (register 22) ................................ ................................ ................................ ........... 34 pvid register (register 23) ................................ ................................ ................................ ............. 35 vpid register (registe r 24) ................................ ................................ ................................ ............. 35 poscfg register (register 25) ................................ ................................ ................................ ........ 35 pause register (register 26) ................................ ................................ ................................ .......... 37 dplx register (register 27) ................................ ................................ ................................ ............ 37 npm register (register 29) ................................ ................................ ................................ ............... 37 errmsk register (register 30) ................................ ................................ ................................ ....... 37 clkadj register (register 31) ................................ ................................ ................................ ........ 37 phyreg register (register 32 - 63) ................................ ................................ ................................ .. 38 8. pin descriptions ................................ ................................ ................................ ..................... 39 rmii clock interface ................................ ................................ ................................ ...................... 40 9. timing description ................................ ................................ ................................ ............... 54 10. electrical specification ................................ ................................ ................................ 60 11. packaging ................................ ................................ ................................ .............................. 61 appendix - a1 ................................ ................................ ................................ ................................ ......... 62 built - in arl with 2048 mac addresses ................................ ................................ ........................ 62
page 3 of 77 confidential page 3 3 1. general description the ACD82224 is a single chip implementation of 24 - port 10/100 ethernet switch system intended for ieee 802.3 and 802.3u compatible ne tworks. the device includes 24 independent 10/100 macs. each mac interfaces with an external pmd/phy device through a reduced mii (rmii ) interface. the last port is rmii and mii selectable. when in mii mode, this port becomes a sha red port with the in - band management cpu. link, speed, and duplex can be automatically configured through the mdio port. each port can operate at either 10mbps or 100mbps. the core logic of the ACD82224, implemented with patent pending basiq ( bandwidth assured switching with intelligent queuing) technology, can simultaneously process 24 asynchronous 10/100mbps port traffic. the queue manager inside the ACD82224 provides the capability of routing traffic with the same order of sequence, without any packet loss. a complete 24 - port 10/100 switch can be built with the addition of 10/100 rmii phy and sram (zbt tm 1 or compatible). an additional 11k mac addresses can be supported with the use of acd?s address resolution logic (arl) chip, the acd80800. advanced network management features can be supported with the use of acd?s management information base (mib) chip, the acd80900. the single universal 388 - pin pbga package for all 3 controllers makes one - pcb - for - all three systems very easy to implement, which significantly reduce the cost and time associated with multiple system product development. figure - 1.1: ACD82224 based 24 ports single chip un - managed 10/100 switch system 1 zbt is the trade mark of idt. zbt sram acd822xx quad rmii phy quad rmii phy quad rmii phy quad rmii phy quad rmii phy mag 23-20 mag 19-16 mag 15-12 mag 11-8 mag 7-4 mag 3-0 led connector sram bus rmii quad phy 4 rmii bus 4 rmii bus 4 rmii bus 4 rmii bus 4 rmii bus 4 rmii bus phys, transformers & rj45 not populated for acd82216 16-port system 100 mhz osc
page 4 of 77 confidential page 4 4 figure - 1.2: ACD82224 based 24 ports 3 - chip managed 10/100 switch system ACD82224 quad rmii phys quad rmii phys quad rmii phys quad rmii phys quad rmii phys quad rmii phys mag 22-20 acd80900 acd80800 optional sram bus text text zbt sram cpu local bus dram flash rs-232 transceiver serial interface crystal mag 19-16 mag 15-12 mag 11-8 mag 7-4 mag 3-0 led connector bus drivers arl bus 4 rmii bus 4 rmii bus 4 rmii bus 4 rmii bus 4 rmii bus rmii bus phys & transformers & rj45 not populated for acd82216 16-port system 3 rmii bus rmii bus 100 mhz osc
page 5 of 77 confidential page 5 5 2. major features 24 ports 10/100 fast ethernet switch (auto - sensing or manual selection) reduced mii interface, with selectable mii for the last port capable of trunking f or up to 800 mbps link full & half duplex operation speed auto negotiation through mdio 4.8 gbps aggregated throughput, true non - blocking switch architecture, full wire speed forwarding built - in storage of 2 ,048 mac address supports up to 11k mac addresses with the acd80800 shared frame buffer with starvation control memory interface with zbt tm or compatible sram at 100mhz automatic source address learning zero - packet los s back - pressure flow control under half duplex mode 802.3x pause frame flow control under full duplex mode store - and - forward switch mode port based v - lan support for up to 4 vlans uart type cpu management interface rmon and snmp support with acd80900 status leds: link, speed, full duplex, transmit, receive, collision, and frame error 388 - pin pbga package power: core 2.5v, i/o 3.3v with 5v tolerance 3 . system block diagram buffer queue manager lookup engine (2k mac addr.) led controller bist handler arl acd80800 (11k mac addr.) (optional) mib acd80900 (optional) arl interface zbt or the compatible sram mac-0 mac-1 mac- (xx-2) mac- (xx-1) sram interface mib interface pmd/ phy-0 pmd/ phy-1 pmd/ phy- (xx-2) pmd/ phy- (xx-1) mx dmx buffer buffer buffer buffer buffer buffer buffer fifo fifo fifo fifo fifo fifo fifo fifo acd822xx xx=16 for acd82216 24 for ACD82224
page 6 of 77 confidential page 6 6 4. system description the ACD82224 is a single chip implementation of a 24 - port fast ethernet switch. together with external sram devices and transceiver devices, it can be used to build a complete 10/100 mbps fast et hernet switch. each port can be either auto - sensing or manually selected to run at 10 mbps or 100 mbps speed rates and under full or half - duplex mode. there are four (4) major functional blocks inside the ACD82224: (a) the media access controller (mac ) (b) the queue manager (c) the lookup engine (d) the register file (e) the mib engine interface there are five (5) types of interfaces: (a) rmii interfaces (b) rmii/mii selectable inte rface (c) memory interface (d) external - arl interface (e) external - mib interface macs, rmii & mii interfaces there are 24 independent macs within the ACD82224. the mac controls the receiving, transmitting, and def erring process of each individual port, in accordance to the ieee 802.3 and 802.3u standards. the mac logic also provides framing, fcs checking, error handling, status indication and flow control functions (backpressure & pause - fr ame). each mac interfaces with an external transceiver through a rmii (reduced mii) interface. the last mac has a selectable rmii/mii interface. the mii mode allows direct connection with the acd80900 (mib), which also acts as a three - port swi tch for the management cpu to share the regular switch port for in - band management. queue manager the device utilizes acd?s proprietary basiq (bandwidth assured switching with intelligent queuing) technology. it efficiently enforce s the first - in - first - out rule of ethernet bridge - type devices. it also enables a true non - blocking frame switching operation at wire speeds for high throughput and high port density ethernet switch design. built - in arl & external - arl interfa ce the on - chip lookup engine implements a 2,048 entries mac address lookup table. it maps each destination address with a corresponding port id. each mac address is automatically learned by the lookup en gine after an error - free frame is received. the address entries can also be managed for aging, locking, and forced filtering. through the serial cpu interface of the ACD82224 switch, a management cpu can learn the address change i n the lookup table. hence, the ACD82224 alone can be used to build a complete fast ethernet switch with up to 2,048 host connections . (see appendix - a for detail) for workgroup or backbone switches, the ACD82224 can support more mac addresses per port through the use of an external arl chip, the acd80800. the ACD82224 has a glueless arl interface that allows a supporting chip (acd80800) to provide up to 11k mac addresses per
page 7 of 77 confidential page 7 7 switch. system designers can also use this arl interface t o implement a vendor - specific address resolution algorithm. register & uart interface a system cpu can access various registers inside the ACD82224 through a serial cpu management interface (uart ) . the cpu can configure the switch by writing into the appropriate registers, or retrieve the status of the switch by reading the corresponding registers within the ACD82224 switch. the cpu can also access the registers of external transceiver (phy) device s through the cpu management interface as well. external - mib & external - mib interface the ACD82224 provides management support through the use of the acd80900 (management information base). the mib interface can be used to monitor all traffic activities of the switch system. the supporting chip (the acd80900) provides a full set of statistics counters to support both snmp and rmon network management functions. in addition to the statistics counters, the acd80900 also support all groups of rmon management, including host, hostn, matrix, filtering and capturing groups. system designers can also use the mib interface to implement vendor - specific network management functionality.
page 8 of 77 confidential page 8 8 5. functional description the mac controller performs transmitting, receiving, and deferring functions, in accordance to the 802.3 and 802.3u specification. the mac logic also handles frame detection, frame generation, error detection, error handling, status indic ation and flow control functions. under full - duplex mode, the flow control is implemented in compliance with ieee 802.3x standard. frame format the ACD82224 assumes that the received data packet will have the followin g format: preamble sfd da sa type/len data fcs where, preamble is a repetitive pattern of ?1010?.? of any length with nibble alignment. sfd (start frame delimiter) is defined as an octet pattern of 10101011. da (de stination address ) is a 48 - bit field that specifies the mac address of the destined dte. for any frame with ?1? in the first bit of the da, with the exception of the bpdu address (the reserved group address described in table 3 - 5 of ieee 802.1d), the ACD82224 will treat it as a broadcast /multicast frame. it will forward the frame to all ports within the source port?s vlan , except the source port itself. sa (source address ) is a 48 - bit field that contains the mac address of the source dte that is transmitting the frame to the ACD82224. after a frame is received with no error , the sa is learned as the port?s mac address. type/len field is a 2 - byte field that specifies the type (dix ethernet frame) or length (ieee 802.3 frame) of the frame. the ACD82224 does not process this information, unless it is a pause - frame data is the encapsulated information within the ethernet packet. the ACD82224 does not process any of the data information in this field. fcs (frame check sequence) is a 32 - bit field of crc (cyclic redundancy check) value based on the destination address, the source address, the type/length and the data field. the acd 82224 will verify the fcs field for each frame. the procedure for computing fcs is described in the section ?fcs calculation.? start of frame detection when a port?s mac logic detects the assertion of the crs_dv signal in the rmii interface, it will start a receiving process. the received data will come through a 2 - bit wide data bus, clocked by the 50 mhz receiving - clock from the ACD82224. it will then pass a frame alignment circuit, which will convert the 2 - bit signal into a si ngle bit stream and detect the occurrence of the sfd pattern (10101011). all signals before the sfd are filtered out and the rest of the data frame will be stored into the frame buffer of the switch. frame reception
page 9 of 77 confidential page 9 9 under normal operating co nditions, the ACD82224 expects a received frame to have a minimum inter frame gap (ifg). the minimum ifg required by the ACD82224 is 64 bt. if a packet comes with an ifg less than 64 bt, the ACD82224 will not guarantee the reception of that frame. the pa cket may be dropped if it is not properly received. the ACD82224 will check all received frames for errors such as symbol error , fcs error, short event, runt, long event, jabber, etc. frames with any kind of error will not be forwarded to any port. preamble bit processing the preamble bit in the header of each frame will be used to synchronize the mac logic with the incoming bit stream. there is no limit on the minimum length or the maximum length of preamble bits. after the receive - signal crs_dv is asserted by the external phy device, the mac will wait for the sfd pattern (10101011) to trigger a frame receiving process. destination address processing as a f rame comes in, the embedded destination address (da) is passed to the address resolution logic (arl ). the arl will compare it with the mac address entries stored in the address lookup table. a destination port is identified if a match of address is found. if external arl is used, the ACD82224 will indicate the present of 48 - bit da through the arl interface. the external arl will use the value of da for address comparison and return a result to the ACD82224 . source address processing as a frame comes in, the embedded source address (sa) will be passed to the arl . at the end of the frame, if no error is detected, the sa will be used t o update the address lookup table. if an external arl is used, the ACD82224 will indicate the presence of a sa on the arl interface, so that the external arl can learn the address. the address table will be cleared after a hardware - reset, but a software - re set will not clear the address table. frame data frame data are transparent to the ACD82224. the ACD82224 will forward the data to destination port(s) without interpreting the content of the frame data field. fcs calculation each port of the ACD82224 has a crc checking logic to verify if the received frame has the correct fcs value. an incorrect fcs value is an indication of a fragmented frame or a frame with frame bit error . the method of calculating the crc val ue is by using the following polynomial, g(x) = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 as a divider to divide the bit sequence of the incoming frame, beginning with the first bit of the destination address field, t o the end of the data field. the result of the calculation, which is the
page 10 of 77 confidential page 10 10 residue after the polynomial division, is the value of the frame check sequence. this value should be equal to the fcs field appended at the end of the frame. if the value does not match the fcs field of the frame, the frame bit error led of the port will be turned on once and the packet will be dropped. illegal frame length & extra - long frame during the receiv ing process, the mac will monitor the length of the received frame. legal ethernet frames should have a length of not less than 64 bytes and no more than 1518 bytes. if the carrier - sense signal (crs_dv) of a frame is asserted for less than 84 b t, the frame is flagged with short event error . if the length of a frame is less than 512 bt, the frame is flagged with runt error. in order to support an application where extra byte length is required, an extra long frame option is provide d. when the extra long frame option is enabled (bit - 11 of register 25) , only frames longer than 1530 bytes are marked with a long event error . frame length is measured from the first byte of da to the last byte of fcs . frame fil tering frames with any kind of error will be filtered. error types include crc, alignment, false carrier sense, short event, runt, long event and jabber. an error frame will still be displayed on the mib interface, along with the error status indication. any frame heading to its own source port will be filtered. when external arl is used, the filtering decision will be made by the arl. the ACD82224 will act in accordance with the arl?s decision. if the spanning tree support option (bit 1 of register 16) is set, a frame with da equal to 01 - 80 - c2 - 00 - 00 - 00 will be forwarded to port - 23 (the default cpu port) as a bpdu frame. if spanning tree support is not enabled, a frame with reserved group address specified in table - 3.5 of the ieee802.1d will be treated as a broadcast frame and will be forwarded to all the ports in the same vlan of the source port. jabber lockup protection if a receiving port is active continuously for more than 50,000 bit times, the port is considered to be jabbering. a jabbering port will automatically be partitioned from the switch system in order to prevent it from impairing the performance of the network. the partitioned port will be re - activated as soon as the offending signal discontinues. excessive collision in the event that there are more than 16 consecutive collisions, the ACD82224 will reset the counter to zero and re - transmit the packet. this implementation insures there is no packet loss even under channel capture situation. however, the ACD82224 has an option to drop the packet on excessive collisions. when this option is enabled (bit - 15 of register 25) , the frame will be dropped after 16 consecutive collisions.
page 11 of 77 confidential page 11 11 frame forwarding if the first bit (bit - 40) of the destination address is 0, the frame is handled as a unicast frame. the destination address is passed to the address resolution logi c; which returns a destination port number to identify which port the frame should be forwarded to. if the address resolution logic cannot find any match for the destination address, the frame will be treated as a frame with unknown da. the frame will be p rocessed in one of two ways upon bit - 12of register 25 . 1. if the option flood - to - all - port is set, the switch will forward the frame to all ports within the same vlan of the source port, except the source port itself. 2. if the option is not set, the frame will be forwarded to the ?dumping port? of the source port vlan only. the dumping port is determined by the vlan id of the source port. if the source port belongs to multiple vlans, a frame with unknown da will then be forwarded to mu ltiple dumping ports of the vlans. if the first bit of the destination address is a 1, the frame is handled as a multicast or broadcast frame. the ACD82224 does not differentiate a multicast packet from a broadcast packet except for the reserved bridge management group address, as specified in table - 3.5 of ieee 802.1d standard. the destination ports of a broadcast frame are all ports within the same vlan except the source port itself. the order of all broadcast frames with respect to the unicast frames is strictly enforced by the ACD82224. frame transmission the ACD82224 transmits all frames in accordance to ieee 802.3 standard. the ACD82224 will send the frames with a guaranteed minimum i nter frame gap of 96 bt, even if the received frames have an ifg less than the minimum requirement. before the transmitting process is started, the mac logic will check if the channel has been silent for more than 64 bt. within the 64 bt silent window, the transmission process will defer on any receiving process. if the channel has been silent for more than 64 bt, the mac will wait an additional 32 bt before starting the transmitting process. in the event that the carrier sense signal is asserte d by the rmii during the wait period, the mac logic will generate a jam signal to cause a forced collision. the mac logic will abort the transmitting process if a collision is detected . re - transmission of the frame i s scheduled in accordance to the ieee 802.3?s truncated binary exponential back - off algorithm. if the transmitting process has encountered 16 consecutive collisions, an excessive collision error is reported, and the ACD82224 will try to re - tr ansmit the frame, unless the drop - on - excessive - collision option of the port is enabled. it will first reset the number of collisions to zero and then start the transmission after a 96 bt of inter frame gap. if drop - on - excessive - collision is enabled, the ac d82224 will not try to re - transmit the frame after 16 consecutive collisions. if collision is detected after 512 bt of the transmission, a late collision error will be reported and the frame may or may not be retransmitted. shared buffer all ports of the ACD82224 work in store - and - forward mode so that all ports can support both 10mbps and 100mbps data speeds. the ACD82224 utilizes a global memory buffer pool, which is shared by all ports. the device has a unique architecture that inherit s the advantages of both output buffer - based and input buffer - based switches: short latency of an output - buffer based switch which only store the received data once into the memory and efficient flow control of an input - buffer based switch.
page 12 of 77 confidential page 12 12 starvation control scheme all frames received by the ACD82224 will be stored into a common physical frame buffer pool. in order to make sure all ports have fair access to the network, a buffer allocation scheme (starvation control) is use d to prevent active ports from occupying all the buffers and starving off the less active ports. the frame buffer pool is divided into 3 portions: the reserved poo l, the common pool and the extra pool , as shown in figure - 5.1: figure - 5.1: buffer partition the reserved pool guarantees each port will have a fair network access possibility, even under the worst traffic congestion situation. it takes about 50% of the total buffer and is evenly allocated to each port as its dedicated buff er slot. the dedicated slot is not shared with other ports. extra pool (shared by all full duplex ports with flow control capability) reserved pool (dedicated to each port) common pool (shared by all the ports) ~50% ~80%
page 13 of 77 confidential page 13 13 the common pool provides a deep buffer for the busy ports (e.g. server port) to serve multiple low speed ports (e.g. client port) simultaneously. it helps to avoid head - of - line bl ocking. it takes about 30% of the total buffer and is shared by all ports. it stores the congested traffics before the flow control mechanism is triggered. the extra pool is reserved only for ports with pause frame based flow control capacit y. it takes the remaining 20% of the total buffer. it is used to minimize the chance of frame dropping by buffering for the latency of the pause frame based flow control scheme. it is used only after a flow control mechanism is triggered. flow control scheme flow control activity is triggered when the buffer utilization exceeds certain thresholds specified by the dedicated registers. register - 10 is used to specify the upper and the lower thresholds of the reserved buffer slot for eac h port. register - 11 is used to specify the upper and the lower thresholds of the broadcast queue. for full duplex with pause frame capability operation: (1) if the buffer utilization of the reserved buffer slot for the sour ce port has exceeded the ?upper threshold?, and the common pool has been used up. (2) then a max - pause - frame (a pause frame with a maximum time interval of ffffh) will be sent to the sending port to stop it from sending any new frames. if pause - frame based flow control is not enabled at that port, the frame will be dropped. (3) once a max - pause - frame is sent, if the utilization of the reserved buffer slot of the port drops below the lower threshold, a mini - pause - frame (a pause frame with minimum time interval of 0) will be sent to the sending port to enable new frame transmission. but if the utilization of the reserved buffer slot of the port does not drop below the lower threshold for the maximum time interval, ACD82224 will not send another max - pause - frame to the sending port to prevent the buffer capturing by other ports. for half duplex operation: (1) if the buffer utilization of a port has exceeded the upper threshold of the reserved buffer slot, and the common pool has been used up. (2) the port will execute backpressure based flow control by sending a jam pattern on each incoming frame. if backpressure flow control of the port is not enabled, the frame will be dropped. if the broadcast flo w control is enabled (when bit - 17 of register - 25 is cleared), flow control will be triggered when the broadcast queue is larger than the ?upper threshold? in register - 11 . all full duplex ports with pause - frame capability will s end a max - pause - frame to its linking party. all half - duplex ports with backpressure capability will jam incoming frames. after a max - pause - frame is sent, and if the broadcast queue is below the ?lower threshold? in register - 11 , a mini - pause - frame will be s ent to release the hold on transmission. port - based vlan support (registers 23 & 24) the ACD82224 can support up to 4 port - based security vlans. each port of the ACD82224 can be assigned to up to four vlan . on power up, every port is assigned to vlan - i as the default
page 14 of 77 confidential page 14 14 vlan. frames from the source port will only be forwarded to destination ports within the same vlan domain. a broadcast /multicast frame will be forwarded to all ports within the vlan( s) of the source port. a unicast frame will be forwarded to the destination port only if the destination port is in the same vlan as the source port. otherwise, the frame will be treated as a frame with unknown da. each vlan can be assigned with a dedicated dumping port. multiple vlans can also share a dumping port. unicast frames with unknown destination addresses will be forwarded to the dumping port of the source port vlan. a leaky vlan can be enabled by setting the correspo nding bit in the system configuration register (bit - 8 of register - 16). a vlan becomes a broadcast domain. each broadcast domain vlan can still be assigned with a dedicated dumping port. port trunking security vl an can be disabled by setting the corresponding bit in the system configuration register (bit 8 of register 16, see table 7.15 ). when security vlan is disabled, each vlan becomes a leaky vlan and is equivalent to a broadcast domain. four dumping ports of four different leaky vlans can be grouped together to form a fat pipe uplink (for example, port 0, port 1, port 2, and port 3 can be grouped to form an 800 mbps uplink port). when multiple dumping ports are grouped as a singl e pipe, each port has to be assigned to one and only one vlan. a unicast frame with a matched da will be forwarded to any destination port, even if the vlan id is different. all unmatched da packets will be forwarded to the desig nated dumping port of the source port vlan. the broadcast and multicast packets will only be forwarded to the ports in the same vlan of the source port. therefore, a 200 to 800 mbps pipe can be established by carefully grouping the dumping ports, and direc tly connecting with any segmentation switches. dumping port each vlan can be assigned with a dedicated dumping port. multiple vlans can share a single dumping port. each dumping port can be used for an up - link connection or for a dte connection. that is, the dumping port can be used to connect the switch with a computer repeater hub, a workgroup switch, a router, or any type of interconnection device compliant with ieee 802.3 standard. ACD82224 will direct t he following frames to the dumping port: (1) a frame with unknown unicast destination address. (2) a frame with a unicast destination address that does not match with any port?s source address within the vlan of the so urce port. (3) a frame with a broadcast /multicast destination address (see spanning tree support). if the device is configured to work under flood - to - all - port mode (register 25, bit 12) , the frames with unknown da will be forwarded to all the ports in the vlan (s) of the source port except the source port itself. mode of operation each port can be configured or auto - sensed to work under either half - duplex or full - duplex mode. under half duplex mode, the csma/cd will be enforced, and the flow control is achieved through backpressure. under full duplex mode, the receiving process and the transmitting process of the port are independent, and the flow control is done by pause - frame based flow control scheme specified by the ieee 802.3x.
page 15 of 77 confidential page 15 15 spanning tree support the ACD82224 supports the spanning tree protocol. when spanning tree support is enabled (register - 16 bit - 1, see tabl e 7.15) , frames from the cpu port (port - 23) having a da value equal to the reserved bridge management group address for bpdu will be forwarded to the port specified by the cpu. frames from all other ports with a da value equal to the reserved g roup address for bpdu will be forwarded to the cpu port if the port is in the same vlan of the cpu port. port 23 is designed as the default cpu port. when spanning tree support is disabled (register - 22 nport register) , all reserved group addre sses for bridge management is treated as broadcast addresses, with the exception of the reserved multicast addresses for pause frame specified by ieee802.3x. every port of the ACD82224 can be set to block - and - listen mode (register - 21 nbp register) through the cpu interface. in this mode, incoming frames with a da value equal to the reserved group address for bpdu will be forwarded to the cpu port. incoming frames with all other da values will be dro pped. outgoing frames with a da value equal to the group address for bpdu will be forwarded to the attached phy device; all other outgoing frames will be filtered. queue management each port of the ACD82224 has its own individual transmission queue. al l frames coming into the ACD82224 are stored into the shared memory buffer, and are lined up in the transmission queues of the corresponding destination port. the order of all frames, unicast or broadcast , is strictly enfo rced by the ACD82224. the ACD82224 is designed with a non - blocking switching architecture. it is capable of achieving wire speed forwarding rates and can handle maximum traffic loads. phy management the ACD82224 supports phy device management through the serial mdio and mdc signal lines. the ACD82224 can continuously poll the status of the phy devices through the serial management interface if register - 25 bit - 16 is cleared. the acd822 24 will also configure the phy capability field like link, speed, and duplex status to ensure proper operation of the link . the ACD82224 also enables the cpu to access any registers in the phy devices through the cpu interface (see register - 32 example). the id of the phy device can start from either ?0? or ?1?, depending on the setting of bit - 14 of register - 25. there are two ways to disable automatic phy management as follows: (1) set register - 25 bit - 16 to disable automatic phy managem ent for all ports. (2) set the specific port in register - 29 to disable the port from automatic phy management. phy interface the phy interface for port - 0 through port - 22 can only be rmii . the rmii clk (50mhz cloc k) will be used as the rxclk and txclk. there are three wires on the receiving side (rxd[1:0] and crs_dv), and three wires on the transmitting side (txd[1:0] and txen). port - 23 can be configured as either rmii or mii (register - 16 bit - 15). the mii option i s used for direct connection with the acd80900 only supporting mii interface. ACD82224 supports phy management through the mdio and mdc signal lines. ACD82224 can continuously poll the status of the phy devices through the serial management i nterface, without
page 16 of 77 confidential page 16 16 using a cpu . ACD82224 also allows the cpu to access any registers in the phy devices through the cpu interface. sram interface the ACD82224 uses pipeline zbt tm (zero - bus - turn - around) or c ompatible types of sram . the speed should be 100mhz or faster. each read or write cycle should take no more than 10 ns. the sram interface contains a 52 - bit data bus (48 - bit data and 4 - bit status), a 19 - bit address bus, and 2 con trol signals. cpu interface the ACD82224 does not require any microprocessor for operation. initialization and most configurations can be done with pull - up or pull - down of designated hardware pins. a cpu interface is provided for a microprocessor to access the internal control registers and status registers. the microprocessor can send a read command to retrieve the status of the switch, or send a write com mand to configure the switch through the interface. the interface is a commonly used uart type interface. the cpu interface can also be used to access the registers inside each phy device connected to the ACD82224. arl interface the ACD82224 has a built - in mac address storage for up to 2,048 source addresses. if more than 2,048 addresses are needed, an external arl (e.g. acd80800) can be used to expand the address space to 11k entries. the external arl is connected through the arl interface (table - 6.9) . it can tap the value if da out of the memory interface bus, and execute a lookup process to map the value of the da into a port number. it can also learn the sa values embedde d in the received frames. the value of sa is used to build the address lookup table inside the acd80800. if the new addressed are over the maximum number of look - up table, arl will not learn the newer address until there is any available entry again (i.e. the learned address aged). mib interface traffic activities on all ports of the ACD82224 can be monitored through the mib interface. through the mib interface, a mib device can view the frames transmitted from or received by any port. therefore, the mib device can maintain a record of traffic statistics for each port to support network management. since all received data are stored into the memory buffer, and all transmitted data are retrieved from the memory bu ffer, the data of the activities can also be captured from the memory interface data bus. the status of each data transaction between the ACD82224 and sram is displayed by dedicated status signals of the ACD82224 interface (table - 6.9) . le d interface the ACD82224 provides a wide variety of led indicators for simple system management. the update of the led is completely autonomous and merely requires low speed ttl or cmos
page 17 of 77 confidential page 17 17 devices as l ed drivers. the status display is designed to be flexible to allow the system designer to choose those indicators appropriate for the specification of the end equipment. there are two led control signals, ledvld0 and ledvld1. they are used to indicate the start and end of the led data signal presented on nled0 - nled3. the ledclk signal is a 2.5 mhz clock signal. the rising edge of ledclk should be used to latch the led data signal into the led driver circuitry. the led data signa ls contain lnk, xmt, rcv, col, err, fdx and spd, which represent link status, transmit status, receive status, collision indication, frame error indication, full duplex operation and operational speed status respectively. these status signals are sent out sequentially from port 23 to port 0, once every 50 ms . for details about the timing diagrams of the led signals, refer to the chapter of ?timing description ? life pulse the ACD82224 will g enerate life pulses at wchdog pin once every 800 nsec to indicate normal operation status. absence of the life pulses is an indication that, the ACD82224 has encountered some fatal error and needs to be reset. the life pulses are used to rese t a watchdog counter, such that, if the watchdog counter is not reset and has reached a predetermined value, a system reset signal can be generated to reset the ACD82224.
page 18 of 77 confidential page 18 18 6. interface description figure - 6.1 shows all the interfaces of the ACD82224 con troller and their relations to other modules in a typical switch system. table - 6.1 list all function pins grouped by types. figure - 6.1 major interface group table - 6.1 interface group interface pin name 82224 rmii port[0:22] pxcrs_dv, pxrxd0, pxrxd1, pxtxen, pxtxd0, and pxtxd1 138 mii port - 23 p23crs*, p23rxdv*, p23rxclk, p23rxerr, p23rxd0*, p23rxd1*, p23rxd2, p23rxd3, p23col,p23txen, p23txd0*, p23txd1*, p23txd2, p23txd3, an d p23txclk (*: shared with rmii signals in port23) 15 rmii clock rmiiclk[5:0] 6 phy management mdc, and mdio 2 memory address addr[0:18] 19 memory data data[47:0], be[2:0], and eof 52 memory control n we, and ncs 2 arl and mib swdir[1:0], swpid[4:0], swsync, swstat[4:0], swrxclk, swtxclk, arldi[3:0], and arldiv 19 led ledvld[1:0], ledclk, and nled[3:0] 7 cpu cpudi, cpudo, and cpuirq 3 system control cl k100, nreset, wchdog, and syserror 4 factory test en16p, clksel, testen, and zbtclk 4 2.5v vdd (for core) 17 3.3v vddq (for i/o) 33 ground vss (including 36 center thermal ground) 67 total number of pins 388 acd822xx zbt sram acd80800 optional acd80900 optional rmii phy led logic system logic led[0:3] ledclk ledvld[0:1] p(a) rmii p23 rmii p(a+1) rmii addr[0:18] ncs data[0:47] clk100 be[0:2] swdir[0:1] swsync swstat[0:3] arldi[0:3] arldiv swrxclk swtxclk p23 rmii eof rmiiclk[0:5] nreset wchdog testen syserr . . . . * a=8 for 82216 0 for 82224 tm nwe
page 19 of 77 confidential page 19 19 rmii interface (rmii) the ACD82224 communicates with the external 10/100 ethernet transceivers through standard rmii interface. the signals of rmii interface are described in table - 6.2a : table - 6.2a: rmii interface name type description pxcrsdv i carrier sense/receive data valid pxrxd0 i receive data bit 0 pxrxd1 i receive data bit 1 pxtxen o transmit enable pxtxd0 o transmit data bit 0 pxtxd1 o transmit data bit 1 rmiiclk[5:0] o reduced mii clock (50 mhz) for rmii interface, signal pxrxdv, pxrxd0, and pxrxd1 are sampled by the rising edge of rmiiclk. signal pxtxen, pxtxd0, and pxtxd1 are clocked out by the falling edge of rmiiclk. the detailed timing requirement is described in the chapt er of ?timing description? mii interface (mii) the last port (e.g. port - 23 on the ACD82224) can be selected to act in mii mode. the mii mode is used to connect the acd80900 for in - band management function. the acd80900 acts as a three - way switch to allow the management cpu to share the regular port. the signals of mii interface are described in table - 6.2b : table - 6.2b: mii interface mii mode rmii mode type description p23crs p23crsdv i carrier sense p23rxdv nc i receive data valid p23rxclk nc i receive clock (25/2.5 mhz) p23rxerr nc i receive error p23rxd0 p23rxd0 i receive data bit 0 p23rxd1 p23rxd1 i receive data bit 1 p23rxd2 nc i receive data b it 2 p23rxd3 nc i receive data bit 3 p23col nc i collision indication p23txen p23txen o transmit data valid p23txclk nc i transmit clock (25/2.5 mhz) p23txd0 p23txd0 o transmit data bit 0 p23txd1 p23txd 1 o transmit data bit 1 p23txd2 nc o transmit data bit 2 p23txd3 nc o transmit data bit 3 under the mii mode, signal p23rxdv, p23rxer and p23rxd0 through p23rxd3 are sampled by the rising edge of p23rxclk. signal p23txen, and p23txd0 th rough p23txd3 are clocked out by the falling edge of p23txclk. the detailed timing requirement is described in the chapter of ?timing description? phy management interface all control and status registers of the p hy devices are accessible through the phy management interface. the interface consists of two signals: mdc and mdio , which are described in table - 6.3 .
page 20 of 77 confidential page 20 20 table - 6.3: phy management interface signals name type description mdc o phy management clock ( 1.25mhz ) mdio i/o phy management data frames transmitted on mdio has the following format ( table - 6.4 ): table - 6.4: mdio format operation pre st op phy - id reg - ad ta data idle write 1?1 01 01 a[4:0] r[4:0] 10 d[15:0] z read 1?1 01 10 a[4:0] r[4:0] z0 d[15:0] z prior to any transaction, the ACD82224 will output thirty - two bits of ?1? as preamble signal. after the preamble, a 01 signal is used to indicate the start of the frame. for a write operation, the device will send a ?01? to signal a write operation. following the ?01? write signal will be the 5 bit id address of the phy device and the 5 bit register address. a ?10? turn around signal is then follows the ?write? signal. after the turn around, the 16 bit of data will be written into the register. after the completion of the write transaction, the line will be left in a high impedance state. for a read operation, the ACD82224 will output a ?10? to indicate read operation after the start of frame indicator. following the ?10? read signal will be the 5 - bit id address of the phy device and the 5 - bit register address. then, the ACD82224 will cease driving the mdio line, and w ait for one bit time. during this time, the mdio should be in a high impedance state. the ACD82224 will then synchronize with the next bit of ?0? driven by the phy device, and continue on to read 16 bits of data from the phy device. the system designer ca n set the id of the phy devices as 0 for port - 0, 1 for port - 1, ? and 23 for port - 23, when the phyid option (bit - 14 of register - 25) is set to ?0?. if the phyid option is set to ?1?, the corresponding phy id should set to 1 through 24. the detail ed timing requirements on phy management signals are described in the chapter of ?timing description.? cpu interface the ACD82224 includes a cpu uart interface to enable an external cpu to acces s the internal registers of the ACD82224. the baud rate of the uart can be from 19200 to 38400 bps. the ACD82224 automatically detects the baud rate for each command, and returns the result at the same baud rate. the signals in the cpu interface are descri bed in table - 6.5 . table - 6.5: cpu interface signals name type description cpudi i cpu data input cpudo tri - state cpu data output cpuirq o cpu interrupt request a comma nd sent by the cpu through the cpudi line consists of 7 octets. command frames transmitted on cpudi have the format shown in table - 6.6 : table - 6.6: cpudi format operation command address index data checksum write 0010xx11 a[7:0] i[7:0] d[23:0] c[7:0]
page 21 of 77 confidential page 21 21 read 0010xx01 a[7:0] i[7:0] d[23:0] c[7:0] the byte order of data in all fields follows the big - endian convention, i.e. most significant octet first. the bit order is the least significant order first. the command octet specifies the type of the operation. the bit - 7, bit - 6, and bit - 5 of the command octet are specified the device type. (1) switch controller, the device type is 001. (2) arl controller, the device type is 010. (3) management controller, the device type is 100. the bit - 2 and bit - 3 of the co mmand octet are used to specify the device id of the chip. they are set by bit 20 and bit 21 of the register 25 at power on strobe. the address octet specifies the number of the register. the index octet specifies the index of the register in a register array. for write operation, the data field is a 3 - octet value to specify what to write into the register. for read operation, the data field is a 3 - octet 0 as padded data. if the data of register is less than 24 - bit, it is aligned to bit - 0 of data field. the checksum value is an 8 - bit value of exclusive - or of all octets in the frame, starting from the command octet. for each valid command received, the ACD82224 will always send a response. response from the ACD82224 is sent throug h the cpudo line. response frames sent by the ACD82224 have the following format ( table - 6.7 ): table - 6.7: switch response format response command result data checksum write 00000011 r[7:0] d[23:0] c[7:0] read 00000001 r[7:0] d[23:0] c[7:0] the command octet specifies the type of the response. the result octet specifies the result of the execution. the result field in a response frame is defined as: ?0? for no error ?1? for access violation error for response to a read operation, the dat a field is a 3 - octet value to indicate the content of the register. for response to a write operation, the data field is 32 bits of 0. if the data of register is less than 24 - bit, it is align to bit - 0 of data field. the checksum value is an 8 - bit value of exclusive - or of all octets in the response frame, starting from the command octet. cpuirq is high active and used to notify the cpu that some special status has been encountered by the ACD82224, like port partition , and fat al system error , etc. by clearing the appropriate bit in the interrupt mask register, the specific source interrupt can be stop. reading the interrupt source register retrieves the source of the interrupt request and clears the interrupt source register. cpuirq keeps high if the interrupt source is still existed. sram interface all received frames are stored into the shared frame buffer through the memory interface. when the destination port is ready to transmit the frame, data is read from the shared memory buffer through the memory interface. the memory interface signals are described in the following table:
page 22 of 77 confidential page 22 22 table - 6.8: zbt sram interface name typ e description data[47:0] i/o memory data bus be[2:0] i/o byte enable eof i/o end of frame addr[18:0] o memory address bus nwe o write enable: 0=write 1=read nce o chip enable, low active the synchronous clock input of the external sram ?s should connect to 100 mhz system clock. data is written into the sram or read from the sram in 52 - bit wide words. addrx specifies the address of each word. data[47:0] are used to transfer up to 6 octets of data each time. be[2:0] indicate the valid bytes in 6 octet of data in data[47:0]. eof indicates the last word of a frame. addr[18:0] specifies up to 512k word addresses. nwe specifies the type of operation for each clock cycle. nce selects the sram chip associated with the word addr ess. the timing requirement for sram access is described in the chapter of ?timing description.? arl & mib interfaces the arl interface provides a communication path between the ACD82224 and an external arl device such as the acd80800, which can provide up to 11k of address lookup. the mib interface provides a communication path between the ACD82224 and an external mib device such as the acd80900 for management function implementa tion. both the acd80800 and the acd80900 collect traffic information by monitoring the data bus of the buffer memory. the two interfaces share many common pins, as shown in figure - 6.1 and table - 6.9. when the ACD82224 receives a frame, it will store it into the frame buffer memory through data bus data[47:0]. the external arl extracts the destination address and source address of the frame posted on the data [0:47] while it is written into the memory. it then finds the corresponding destination port and retu rns the result through the arldi[3:0] lines to the ACD82224. the timing requirement on arl signals is described in chapter 9, ?timing description?. at the same time, the external mib also grabs the frame into its internal buffer for further management processing. please see the acd80800 and the acd80900 data sheets for details.
page 23 of 77 confidential page 23 23 table - 6.9: arl & mib interfaces signals name type arl interface mib interface data[47:0] o frame data be[2:0] o byte enable : be[0:2] eof o end of frame: eof swdir[1:0] o data direction indicator : 00 = idle, 01 = receive, 10 = transmit, 11 = control swsync o port synchronization: indicating when port - 0 is driving dat[0:47] swstat[3:0] o data state indicat or: 0000 ? idle 0001 ? first word (da) 0010 ? second word (sa) 0011 ? third through last word 0100 ? filter event 0101 ? drop event 0110 ? jabber 0111 ? false carrier (receive) - deferred transmission (transmit) 1000 ? alignment er ror (receive) - single collision (transmit) 1001 ? flow control (receive) - multiple collision (transmit) 1010 ? short event (receive) - excessive collision (transmi t) 1011 ? runt (receive) - late collision (transmit) 1100 ? symbol error 1101 ? fcs error 1110 ? long event 1111 ? reserved swrxclk o receive clock swtxclk o na transmit clock p - 23 mii na the default cpu port, share with regular port - 23 traffic arldi[3:0] i arl data input: returns 12 - bit (3 - cycles) arl look - up result to the switch: bit[11:7] - source port id (0 - 23) bit[6:5] ? look - up result: 00 ? reserved 01 ? matched 10 ? not matched 11 ? forced discard bit[4:0] - destination port id (0 - 23) na arldiv i arl data input valid: assertion to indicate start of a new result on arldi[0:3] na led interface the status of each port is displayed on the led interface for every 50ms. ledvld0 and ledvld1 are used to indicate the start and end of the led data. led data is clocked out by the
page 24 of 77 confidential page 24 24 falling edge of ledclk, and should be sampled by the rising edge of ledclk. led data of port - 23 are clocked ou t first, followed by port - 22 down to port - 0. all led signals are low active. the signals in the led interface is described in table - 6.10 : table - 6.10: led interface signals name type description group 0 group 1 ledvld0 o led signal valid 0 1 0 ledvld1 o led signal valid 1 0 1 ledclk o 2.5 mhz led clock - - nled0 o dual purpose indicator na frame error indicator nled1 o dual purpose indicator full duplex indication collision indication nled2 o dual purpose indicator port speed (1=10mbps,0=100mbps) receiving activity nled3 o dual purpose indicator link status transmit activity
page 25 of 77 confidential page 25 25 configuration interface the default values of certain register bits are set by internal pull - high/pull - low 75k ohm resistors. these default values can be overwritten by external pull - high/pull - low with 4.7k ohm resistors. table - 6.11 lists all the available pins. the meanings of the register bits are described in the chapter of ?register description.? table - 6.11: configuration interface pos# pin name register bit# default 0 p20txd0 0 1 p20txd 1 1 2 p21txd0 2 3 p21txd1 3 4 p17txd0 4 5 p17txd1 5 6 p18txd0 6 7 p18txd1 7 8 p20txen 8 9 p21txen 9 10 p17txen 10 11 p18txen 11 12 ledclk 12 13 ledvld0 13 14 ledvld1 14 15 nled3 15 16 nled2 16 17 nled1 17 18 nled0 18 19 p15txen 19 20 p12txen, 20 21 p14txen 21 22 p23txen 22 23 p11txen register - 25 23 table - 7.25 24 p03txen register - 16 15 table - 7.16 25 p23txd0 0 26 p23txd1 1 27 p23txd2 2 28 p23txd3 3 29 p05txen 4 30 p06txen 5 31 p08txen 6 32 p09txen register - 31 7 table - 7.31 33 p00txd0 0 34 p00txd1 1 35 p02txd0 2 36 p02txd1 3 37 p03txd0 4 38 p03txd1 5 39 p05txd0 6 40 p05txd1 register - 30 7 table - 7.30 41 p00txen 1 0 42 p02txe n register - 20 of the built - in arl 2 0 note: pos41 and pos42 are belonging to build - in arl?s poscfg register (arl register 20).
page 26 of 77 confidential page 26 26 other interface table - 6.12: other signals name type description clk100 i 100 mhz clock input nreset i hardware reset, low active wchd og o watch dog life pulse syserror o system error indication zbtclk o factory use only clksel, en16p, testen i factory use only vdd i 3.3v power vddc i 2.5v power vss i ground the clk100 should come from 100mhz clock oscillator, with 3.3volt or 5volt, 40/60 duty cycle, and 50 ppm accuracy. the nreset is a low - active hardware reset pin. assertion of this pin will cause the ACD82224 to go through a power - up initialization process. all registe rs are set to their default value after reset. the wchdog pin is used to handle exceptional cases. a normal working ACD82224 sends out continuous life pulses from the wchdog pin, which can be monitored by an external watchdog circuit. if no life pulse is detected, the external watchdog circuit may force reset of the switch system. it is a safeguard against unforeseeable situations. the syserror is system error indication and it?s high active. when there is any error occurs in syserr register it?s asserted to high until the syserr register been read. the clksel, en16p, and testen are input pins for factory test use only. these three pins must be connected to ground directly. the zbtclk is output pin and also for factory use. do not connect th e zbtclk.
page 27 of 77 confidential page 27 27 7. register description registers in the ACD82224 are used to define the operational mode of various function modules of the switch controller and the peripheral devices. default values at power - on are predefined. the management cpu (optional) can read the content of all registers and modify some of the registers to change the operational mode. table - 7.0.1 lists all the registers inside the switch controller. table - 7.0.1: register list address name type size index descrip tion 0 devid r 16 bit 1 device id is 0601h 1 intsrc r 8 bit 1 interrupt source 2 syserr r 9 bit 1 system error 3 par r 24 bit 1 port partition indication 4 pmerr r 24 bit 1 phy management error 5 act r 24 bit 1 port acti vity 6 rsvd r - - - 7 rsvd r - - - 8 sal r/w 24 bit 1 source address , bit 23:0 9 sah r/w 24 bit 1 source address , bit 47:24 10 uth r/w 16 bit 1 unicast threshold 11 bth r/w 16 bit 1 broadcast threshold 12 ma xl r/w 16 bit 1 fcs of max - pause - frame , bit 15:0 13 maxh r/w 16 bit 1 fcs of max - pause - frame , bit 31:16 14 minl r/w 16 bit 1 fcs of mini - pause - frame , bit 15:0 15 minh r/w 16 bit 1 fcs of mini - pause - frame , bi t 31:16 16 syscfg r/w 16 bit 1 system configuration 17 intmsk r/w 8 bit 1 interrupt mask 18 speed r/w 24 bit 1 port speed 19 link r/w 24 bit 1 port link 20 nfwd r/w 24 bit 1 port forward disable 21 nbp r/w 24 bit 1 port back pre ssure disable 22 nport r/w 24 bit 1 port disable 23 pvid r/w 4 bit 24 port vlan id 24 vpid r/w 5 bit 4 vlan dumping port 25 poscfg r/w 24 bit 1 power - on - strobe configuration 26 pau se r/w 24 bit 1 port pause frame disable 27 dplx r/w 24 bit 1 port duplex mode 28 rsvd r - - - 29 npm r/w 24 bit 1 port phy management disable 30 errmsk r/w 8 bit 1 error mask 31 clkadj r/w 8 bit 1 arl clock d elay adjustment 32~63 phyreg r/w 16 bit 32 registers in phy device with id is 0~31
page 28 of 77 confidential page 28 28 many registers have particular bit designated to a particular port, so that the status of each port can be changed or monitored independently. the mapping of register - b it and port - id for each controller is listed in table - 7.0.2. table - 7.0.2: register - bit/port - id mapping register ? bit port ? id port number ACD82224 0 0 port 0 1 1 port 1 2 2 port 2 3 3 port 3 4 4 port 4 5 5 port 5 6 6 port 6 7 7 port 7 8 8 port 8 9 9 port 9 10 10 port 10 11 11 port 11 12 12 port 12 13 13 port 13 14 14 port 14 15 15 port 15 16 16 port 16 17 17 port 17 18 18 port 18 19 19 port 19 20 20 port 20 21 21 port 21 22 22 port 22 23 23 port 23 intsrc register (register 1) the intsrc register indicates the source of the interrupt request. before the cpu starts to respond to an interrupt request, it should read this register to find out the interrupt source. this regis ter is automatically cleared after each read. table - 7.1 lists all the bits of this register. table - 7.1: intsrc register bit description default 0 system initialization completed 0 1 system error occurred 2 port partition oc curred 3 arl interrupt 4 reserved 5 6 7 note: the source interrupt for bit - 3 arl interrupt is referred to arl register - 13.
page 29 of 77 confidential page 29 29 syserr register (register 2) the syserr register indicates the presence of system errors . i t is automatically cleared after each read. table - 7.2 lists the system error reported . table - 7.2: syserr register bit description default 0 bist failure indication 0 1 reserved 2 3 4 5 6 7 8 par register (register 3) the par register indicates the presence of the partitioned ports and the port id . a port can be automatically partitioned if there is a consecutive false carrier event, an excessive collision or jabber. this register is auto matically cleared after each read. table - 7.3 lists the bits of this register. table - 7.3: par register bit description default [0:23] 0 ? port x is not partitioned . 1 ? port x is partitioned . 0 pmerr register (regist er 4) the pmerr register indicates the presence of phys that have failed to respond to the phy management command issued through the mdio line. this register is automatically cleared after each read. table - 7.4 describes the bits of this register. table - 7.4: pmerr register bit description default [0:23] 0 ? port x?s phy responded 1 ? port x?s phy failed to respond 0 act register (register 5) the act register indicates the presence of transmitting or receiving activ ities of each port since the register was last read. this register is automatically cleared after each read. table - 7.5 describes all the bits of this register. table - 7.5: act register bit description default [0:23] 0 ? port x no activity 1 ? port x has activity 0
page 30 of 77 confidential page 30 30 sal & sah register (register 8,9) the sal and sah registers together contain the complete source address for pause frame generation. sal contains the least significant 24 bit of the mac address. sah contains the most significant 24 bit of the mac address. the default locally managed source address for pause frame generation is feh - ffh - ffh - ffh - ffh - ffh a. table - 7.8 and table - 7.9 describes all the bits of these two registers. table - 7.8: sal register bi t description default 7:0 bit 47:40 of the switch?s mac address. feh 15:8 bit 39:32 of the switch?s mac address. ffh 23:16 bit 31:24 of the switch?s mac address. table - 7.9: sah register bit description default 7:0 b it 23:16 of the switch?s mac address. ffh 15:8 bit 15:8 of the switch?s mac address. 23:16 bit 7:0 of the switch?s mac address. uth register (register 10) the uth register contains the unicast buffer thresholds for each port. when the upper threshold is exceeded, the mac may generate a max - pause - frame . when the lower threshold is crossed, the mac may generate a mini - pause - frame . table - 7.10 describes each bit in this register. tab le - 7.10: uth register bit description total frame buffer depth (52 - bit wide word) default* 7:0 lower threshold of unicast utilization. 64k 128k 256k 512k 2 4 8 16 15:8 higher threshold of unicast utilization. 6 4k 128k 256k 512k 4 8 24 64 * note: the value is related to the memory size specified by bit[9:8] of register 25.
page 31 of 77 confidential page 31 31 bth register (register 11) the bth register contains the broadcast queue buffer threshold for each port. when the upper t hreshold is exceeded, the mac may generate a max - pause - fra me. when the lower threshold is crossed, the mac may generate a mini - pause - frame . table - 7.11 describes each bit in this register. table - 7.11: bth register bit description defa ult 7:0 lower threshold of broadcast queue 16 15:8 higher threshold of broadcast queue 48 minl & minh register (register 12,13) the minl and minh registers together contain the 32 - bit frame check sequence (fcs ) of the mini - pause - frame. minl contains the least significant 16 bit of the fcs. minh contains the most significant 16 bit of the fcs. the default fcs value assumes the default source address for the mini - pause - frame . table - 7.12 and table - 7. 13 describe all the bits of these two registers. table - 7.12: minl register bit description default 7:0 bit 31:24 of the mini - pause - frame?s fcs 89 15:8 bit 23:16 of the mini - pause - frame?s fcs o3 table - 7.13: m inh register bit description default 7:0 bit 15:18 of the mini - pause - frame?s fcs d7 15:8 bit 7:0 of the mini - pause - frame?s fcs a9 maxl & maxh register (register 14,15) the maxl and maxh registers together c ontain the 32 - bit frame check sequence (fcs ) of the max - pause - frame. maxl contains the least significant 16 bit of the fcs. maxh contains the most significant 16 bit of the fcs. the default fcs value assumes the default source address for the max - pause - frame . table - 7.14 and table - 7.15 describe all the bits of these two registers. table - 7.14: maxl register bit description default 7:0 bit 31:24 of the max - pause - frame?s fcs 0d 15:8 bit 23:16 of the max - pause - frame?s fcs 68 table - 7.15: maxh register bit description default 7:0 bit 15:8 of the max - pause - frame?s fcs d8 15:8 bit 7:0 of the max - pause - frame?s fcs d0
page 32 of 77 confidential page 32 32 syscfg register (register 16) the syscfg register specifies certain system configurations . the system options are described in the chapter of ?function description.? table - 7.16 describes all the bits of this register. table - 7.16: syscfg register bit description default 0 0 ? bist enabled; 1 ? bist disabled. 0 1 0 ? spanning tree support disabled; 1 ? spanning tree support enabled 2 0 ? external arl result latched by rising edge; 1 ? external arl result latched by fall ing edge; 3 reserved. 4 reserved. 5 0 ? wait for cpu . 1 ? system ready to start *this bit is used by the cpu when bit - 15 of register - 25 is set as ?0? (for system with control cpu). the system will wait for cpu to set this bit. m ust set this bit before cpu programs any register. 6 0 ? phy management not completed 1 ? phy management completed. *this bit is used by the cpu when bit - 15 of register - 25 is set as ?0? (for system with a control cpu). the mac will not start until this bit is set by the cpu. 7 0 ? watchdog function enabled. 1 ? watchdog function disabled. 8 0 ? secure vlan checking rule enforced. 1 ? leaky vlan checking rule enforced . 9 reserved. 10 0 ? late back - pressure scheme disabled 1 ? late back - pressure scheme enabled *when enabled, the mac will generate back - pressure only after reading the first bit of da 11 0 ? special handling of broadcast frames disabled 1 ? special handling of broadcast frames enabled *when enabled, all broadcast frames from port0~port22 are forwarded to the port23 only, and all broadcast frames from the port23 are forwarded to all other ports. 12 software reset: set ?1? to start a system reset to initialize all state machines. it will not re - start phy's auto - negotiation. 13 hardware reset: set ?1? to stop the life pulse on the watchdog pin, which in turn wil l trigger the external watchdog circuitry to reset the whole system. 14 reserved 15 0 ? port 23 is mii 1 ? port 23 is rmii (pos shared with p03txen) 1 if the bit - 19 of register - 25 is set (cpu start mode), ACD82224 will stop the initialized procedures after it is completed with self - test. cpu must set bit - 5 of register - 16 to enable access internal registers. cpu set bit - 6 of register - 16 to enable mac and queue manager. then ACD82224 will start switching based on cpu?s configuration.
page 33 of 77 confidential page 33 33 intms k register (register 17) the intmsk register defines the valid interrupt sources allowed to assert interrupt request pin. table - 7.17 lists all the bits of this register. table - 7.17: intmsk register bit description default 0 enable ?syste m initialization completion? to interrupt 1 1 enable ?internal system error ? to interrupt 2 enable ?port partition event? to interrupt 3 enable ?internal arl? to interrupt 4 reserved 5 6 7 speed register (register 18) the speed register specifies or indicates the speed rate of each port. table - 7.18 describes all the bits of this register. these two modes are also applied to the speed (register - 18) , link (register - 19), dplx (register - 27), pause (register - 26) register. (1) automatic phy management mode (default setting): these four registers controlled by ACD82224's phy management hardware update their status. to enable this mode if bit - 16 of register - 2 5 is cleared, and the corresponding bit (port) in npm register (register - 29) is cleared. (2) cpu mode: cpu sets these registers through uart interface. to enable this mode if bit - 16 of register - 25 is set, or the corresponding bit (port) in npm register (regis ter - 29) is set. table - 7.18: speed register bit description default [0:23] 0 ? port x at 10mbps 1 ? port x at 100mbps 0 link register (register 19) the link register specifies or indicates the link status of each port. table - 7.19 describes all the bits of this register. table - 7.19: link register bit description default [0:23] 0 ? port x link not established 1 ? port x link established 0
page 34 of 77 confidential page 34 34 nfwd register (register 20) the nfwd register defines the forwarding mode of each port. under forwarding mode, a port can forward all frames. under block - and - listen mode, a port will not forward regular frames, except bpdu frames. if the spanning tree algorithm discovers redundant links, the control cpu will allow only one link remaining in forwarding mode and force the other links into block - and - listen mode. setting the associated bit in this register will put the port into block - and - listen mode. table - 7.20 describes all the bits of this register. table - 7.20: nfwd register bit description default [0:23] 0 ? port x in forwarding state. 1 ? port x in block - and - listen state. 0 nbp register (register 21) the nbp register defines backpressure flow control capability for each port. table - 7.21 describes all the bits of this register. table - 7.21: nbp register bit description default [0:23] 0 ? port x back - pressure scheme enabled 1 ? port x back pressure scheme disabled 0 nport register (register 22) the nport register is used to isolate ports from the network. setting the associated bit in this register will stop a port from either receiving or transmitting any frame. table - 7.22 describes all the bits of this register. but, the source mac address is still learned by arl unless arl nlearnreg is set for the specific port. table - 7.22: nport register bit description default [0:23] 0 ? port x enabled 1 ? port x disabled 0
page 35 of 77 confidential page 35 35 pvid register (regi ster 23) the pvid registers assign vlan ids for each port. there are 24 pvid registers, one for each port. a pvid consists of 4 bits, each corresponding bit mapping to one of the 4 vlans. a port can belong to more than one vlan at the same time . table - 7.23 describes all the bits of this register. table - 7.23: pvid register bit description default default port 1~23 (index = 1~23) port 0 (index = 0) 0 0 ? port not in vlan - i. 1 ? port in vlan - i. 1 1 1 0 ? port not in v lan - ii. 1 ? port in vlan - ii. 0 1 2 0 ? port not in vlan - iii. 1 ? port in vlan - iii. 0 1 3 0 ? port not in vlan - iv. 1 ? port in vlan - iv. 0 1 vpid register (register 24) the vpid regist ers specify the dumping port for each vlan . there are 4 vpid 5 - bit registers, one for each vlan. a valid vpid's id is ?0? through ?23". table - 7.24 describes all the bits of this register. if the multiple vlans are set, the dumping port for the a ssociated vlan has to be assigned correctly even bit - 12 of register - 25 is set ( unknown da forwarded to all ports ). table - 7.24: vpid registers (4 registers) vpid register index bit description default vpid[0] 0 4:0 dumping port id for vlan - 1 ?00000? vpid[1] 1 4:0 dumping port id for vlan - 2 port - 0 vpid[2] 2 4:0 dumping port id for vlan - 3 vpid[3 3 4:0 dumping port id for vlan - 4 poscfg register (register 2 5) the poscfg register specifies a certain configuration setting for the switch system. the default values of this register can be changed through pull - up /pull - down of specific pins, as described in the ?configuration interface ? section of the ?interface description? chapter. table - 7.25 describes all the bits of this register.
page 36 of 77 confidential page 36 36 table - 7.25: poscfg register bit description default shared pin 3:0 zbt sram read timing adjustment (16 levels within a 10 ns clock cycle, each delay unit adds approximately 0.5 - 0.7 ns, ?inversion? adds 5 ns or one half of clock cycle to the delay) 0000 p21txd1 p21txd0 p20txd1 p20txd0 0001 ? no delay 0011 ? 1 units delay 0101 ? 2 units delay 0111 ? 3 units delay 1001 ? 4 units delay 1011 ? 5 units delay 1101 ? 6 units delay 1111 ? 7 units delay 0000 ? inversion plus no delay 0010 ? inversion plus 1 units delay 0100 ? inversion plus 2 units delay 0110 ? inversion plus 3 units delay 1000 ? inversion plus 4 units delay 1010 ? inversion plus 5 units delay 1100 ? inversion plus 6 units delay 1110 ? inversion plus 7 units delay (from bit3 to bit0) 7:4 zbt sram clock timing adjustment (16 levels within a 10 ns clock cycle, each delay unit adds approximately 0.5 - 0.7 ns, ?inversion? adds 5 ns or one half of clock cycle to the delay) 0000 p18txd1 p18txd0 p17txd1 p17txd0 0101 ? no delay 0111 ? 1 units delay 0001 ? 2 units delay 0011 ? 3 units delay 1101 ? 4 units delay 1111 ? 5 units delay 1001 ? 6 units delay 1011 ? 7 units delay 0100 ? inversion plus no delay 0110 ? inversion plus 1 units delay 0000 ? inversion plus 2 units delay 0010 ? inversion plus 3 units delay 1100 ? inversion plus 4 units delay 1110 ? inversion plus 5 units delay 1000 ? inversion plus 6 units delay 1010 ? inversion plus 7 units delay 9:8 sram size selection: 00 ? 64k words 01 ? 128k words 10 ? 256k words 11 ? 512k words 01 p21txen p20txen 10 0 ? mdc latched by rising edge; 1 ? mdc latched by falling edge; 0 p17txen 11 0 ? long event defined as frame longer than 1518 byte. 1 ? long event defined as frame longer than 1530 byte. 1 p18txen 12 0 ? frames with unknown da forwarded to the dumping port. 1 ? frames with unk nown da forwarded to all ports. 0 ledlck 13 0 ? internal arl selected (2k mac address entry). 1 - external arl selected (11k mac address entry). 0 ledvld0 14 0 ? phy ids start from 0, range from 1 to 23. 1 ? phy id s start from 1, range from 0 to 24 0 ledcld1 15 0 ? re - transmit after excessive collision. 1 ? drop after excessive collision. 0 nled3 16 0 ? automatic phy management enabled 1 ? automatic phy management disable d: cpu need to update speed, link, dplx and pause registers 0 nled2 17 0 ? flow control on broadcast queue utilization enabled 1 ? flow control on broadcast queue utilization disabled: broadc ast frames dropped if the queue is full 0 nled1 18 0 ? system errors will trigger software reset 1 ? system errors will trigger hardware reset 0 nled0 19 0 ? system will start by itself upon hardware reset 1 ? system will not st art until bit - 5/6 of register - 16 is set 0 p15txen 21:20 2 - bit device id for uart communication. the device responses only to uart commands with matching id 0 p14txen p12txen 22 0 ? rmii tx?s data is driven on falling edge 1 ? rmii tx?s data is driven on rising edge 1 p23txen 23 0 ? rmii rx?s data is latched on rising edge 1 ? rmii rx?s data is latched on falling edge 1 p11txen
page 37 of 77 confidential page 37 37 pause register (register 26) the pause register defines the p ause - frame based flow control capability of each port. table - 7.26 describes all the bits of this register. table - 7.26: pause register bit description default [0:23] 0 ? port x pause - frame disabled 0 1 ? port x pause - frame enabled dplx register (register 27) the dplx register specifies or indicates the half/full - duplex mode of each port. table - 7.27 describes all the bits of this register. table - 7.27: dplx register bit description default [0:23] 0 ? port x under half dupl ex mode 0 1 ? port x under full duplex mode npm register (register 29) the npm register indicates the automatic phy management capability of each port. if a bit is set in this register, the corresponding speed, link, dplx, and pause registers of the port will not be updated by automatic phy management. table - 7.29 describes all the bits of this register. table - 7.29: npm register bit description default [0:23] 0 ? port x?s status update enabled 0 1 ? port x?s status updat e disabled errmsk register (register 30) the errmsk register defines certain errors as system errors . it is reserved for factory use only. table - 7.30 lists all the error masks specified by this register. table - 7.30: errmsk reg ister bit description default shared pin 0 reserved 1 p00txd0 1 reserved 1 p00txd1 2 reserved 1 p02txd0 3 reserved 1 p02txd1 4 reserved 1 p03txd0 5 reserved 1 p03txd1 6 reserved 1 p05txd0 7 reserved 1 p05txd1 clkadj register (register 31) the c lkadj register defines the delay time of the arlclk relative to the transition edge of the data signals. the arlclk provides reference timing for supporting chips, such as the
page 38 of 77 confidential page 38 38 acd80800 and the acd80900, which need to snoop the data bus for certain activiti es. table - 7.31 describes all the bits of this register. table - 7.31: clkadj register bit description default shared pin 3:0 arl clock timing adjustment: (16 levels within a 10 ns clock cycle, each delay unit adds approximately 0.5 - 0.7 ns, ?in version? adds 5 ns or one half of clock cycle to the delay) 0011 p23txd3 p23txd2 p23txd1 p23txd0 0001 ? no delay 0011 ? 1 units delay 0101 ? 2 units delay 0111 ? 3 units delay 1001 ? 4 units delay 1011 ? 5 units delay 1101 ? 6 units delay 1111 ? 7 units delay 0000 ? inversion plus no delay 0010 ? inversion plus 1 units delay 0100 ? inversion plus 2 units delay 0110 ? inversion plus 3 units delay 1000 ? inversion plus 4 units delay 1010 ? inversion plus 5 units delay 1100 ? inversion plus 6 units delay 111 0 ? inversion plus 7 units delay (from bit3 to bit0) 5:4 write data window width adjustment 00 p06txen (approximately 0.7 ns per increment) 00 ? default 2.5 ns wide 01 ? 1 units increment 10 ? 2 units increment 11 ? 3 units increment p05txen 7:6 wr ite data window location adjustment 00 p09txen (approximately 1.25ns per increment) 00 ? no delay 01 ? 1 unit delay 10 ? 2 units delay 11 ? 3 units delay p08txen phyreg register (register 32 - 63) the phyreg refers to the registers residing on the ph y devices. the ACD82224 provides a mirror access path for the control of cpu to access the registers on the phys. for detailed information about the phy registers, please refer to the phy data sheet. the register index is used by the ACD82224 to specify the phy's internal registers. for example, register - 36 with index - 0 would refer to the control register (register - 0) in the device of phy's id is 4. table - 7.24: phy registers phyreg 32~63 index description default register 32 0~31 phy managem ent registers with phy's id is 0 phy register 33 0~31 phy management registers with phy's id is 1 default register 34 0~31 phy management registers with phy's id is 2 value register 35 0~31 phy management registers with phy's id is 3 .. .. .. .. .. .. register 63 0~31 phy management registers with phy's id is 31
page 39 of 77 confidential page 39 39 8. pin descriptions figure - 8.1: pin diagram/bottom view aa ab ac ad ae af 2 4 6 8 10 12 14 16 18 20 22 24 26 1 3 5 7 9 11 13 15 17 19 21 23 25 a b c d e f g h j k l m n p r t u v w y
page 40 of 77 confidential page 40 40 rmii clock interface pin name location i/o description rmiiclk0 rmiiclk1 rmiiclk 2 rmiiclk3 rmiiclk4 rmiiclk5 ac07 af16 ae24 v24 j25 c23 o reduced mii clock (50 mhz) rmii interface (port 0 ~ port 22) pin name location i/o description p00crs_dv ae10 i carrier sense/receive data valid p00rxd0 af10 i receive data bit 0 p 00rxd1 ac10 i receive data bit 1 p00txd0 ac09 i/o* transmit data bit 0 errmsk reg bit - 0: reserved (default high) p00txd1 ad08 i/o* transmit data bit 1 errmsk reg bit - 1: reserved (default high) p00txen ad07 i/o* transmit enable arl?s poscfg reg bit - 1: no cpu mode (default low). suggest pull - high with 4.7k resister to set nocpu enabled. p01crs_dv ae12 i carrier sense/receive data valid p01rxd0 af12 i receive data bit 0 p01rxd1 ad11 i receive data bit 1 p01txd0 ad10 o transmit data bit 0 p01txd1 af11 o transmit data bit 1 p01txen ae11 i/o* transmit enable arl?s poscfg reg bit - 2: reserved (default low). p02crs_dv ad12 i carrier sense/receive data valid p02rxd0 ae14 i receive data bit 0 p02rxd1 ac14 i receive data bit 1 p02txd0 ac12 i/o* transmit data bit 0 errmsk reg bit - 2: reserved (default high) p02txd1 af13 i/o* transmit data bit 1 errmsk reg bit - 3: reserved (default high) p02txen ae13 o transmit enable p03crs_dv ad14 i carrier sense/receive data valid p03rxd0 ae16 i receive data bit 0 p03rxd1 ad15 i receive data bit 1 p03txd0 ad13 i/o* transmit data bit 0 errmsk reg bit - 4: reserved (default high) p03txd1 ae15 i/o* transmit data bit 1 errmsk reg bit - 5: in: reserved (default high) p03txen af14 i/o* transmit enable syscfg reg bit - 15: port23 mi i/rmii selection. (default high) p04crs_dv ac17 i carrier sense/receive data valid p04rxd0 ae18 i receive data bit 0 p04rxd1 ad17 i receive data bit 1 p04txd0 ad16 o transmit data bit 0 p04txd1 af17 o transmit data bit 1 p04txen ac15 o transmit enabl e p05crs_dv ad18 i carrier sense/receive data valid p05rxd0 ae20 i receive data bit 0 p05rxd1 ac19 i receive data bit 1 p05txd0 ae19 i/o* transmit data bit 0
page 41 of 77 confidential page 41 41 errmsk reg bit - 6 (default high) p05txd1 af19 i/o* transmit data bit 1 errmsk reg bit - 7 (defa ult high) p05txen af18 i/o* transmit enable (default low) clkadj reg bit - 4: write data window width adjustment bit - 0 p06crs_dv af21 i carrier sense/receive data valid p06rxd0 ad20 i receive data bit 0 p06rxd1 ae22 i receive data bit 1 p06txd0 ad19 o t ransmit data bit 0 p06txd1 ae21 o transmit data bit 1 p06txen af20 i/o* transmit enable (default low) clkadj reg bit - 5: write data window width adjustment bit - 1 p07crs_dv ac22 i carrier sense/receive data valid p07rxd0 af23 i receive data bit 0 p07rxd 1 ad22 i receive data bit 1 p07txd0 ad21 o transmit data bit 0 p07txd1 ae23 o transmit data bit 1 p07txen af22 o transmit enable p08crs_dv ad25 i carrier sense/receive data valid p08rxd0 ad26 i receive data bit 0 p08rxd1 ac25 i receive data bit 1 p0 8txd0 af24 o transmit data bit 0 p08txd1 ae26 o transmit data bit 1 p08txen ad23 i/o* transmit enable clkadj reg bit - 6: write data window location adjustment. bit - 0 (default low) p09crs_dv ab23 i carrier sense/receive data valid p09rxd0 ab24 i receive data bit 0 p09rxd1 y23 i receive data bit 1 p09txd0 ac26 o transmit data bit 0 p09txd1 ab25 o transmit data bit 1 p09txen ac24 i/o* transmit enable clkadj reg bit - 7: write data window location adjustment. bit - 1 (default low) p10crs_dv y26 i carrier sense/receive data valid p10rxd0 y24 i receive data bit 0 p10rxd1 w25 i receive data bit 1 p10txd0 aa26 o transmit data bit 0 p10txd1 y25 o transmit data bit 1 p10txen aa24 o transmit enable p11crs_dv v25 i carrier sense/receive data valid p11rxd0 v 26 i receive data bit 0 p11rxd1 u25 i receive data bit 1 p11txd0 w26 o transmit data bit 0 p11txd1 w24 o transmit data bit 1 p11txen v23 i/o* transmit enable pos reg bit - 23: rmii rx?s data is latched on falling edge/rising edge(default high), suggest pull - low with 4.7k resister. p12crs_dv u24 i carrier sense/receive data valid p12rxd0 r25 i receive data bit 0 p12rxd1 r26 i receive data bit 1 p12txd0 u23 o transmit data bit 0 p12txd1 t25 o transmit data bit 1 p12txen u26 i/o* transmit enable (defa ult low)
page 42 of 77 confidential page 42 42 pos reg bit - 20: 2 - bit device id bit - 0 for uart communication. ACD82224 responses only to uart commands with matching id. p13crs_dv r24 i carrier sense/receive data valid p13rxd0 n23 i receive data bit 0 p13rxd1 n26 i receive data bit 1 p13txd 0 r23 o transmit data bit 0 p13txd1 p26 o transmit data bit 1 p13txen p25 o transmit enable p14crs_dv m26 i carrier sense/receive data valid p14rxd0 l25 i receive data bit 0 p14rxd1 m24 i receive data bit 1 p14txd0 m25 o transmit data bit 0 p14txd1 n24 o transmit data bit 1 p14txen p24 i/o* transmit enable (default low) pos reg bit - 21: 2 - bit device id bit - 1for uart communication. the device responses only to uart commands with matching id. p15crs_dv l24 i carrier sense/receive data valid p15rxd0 k26 i receive data bit 0 p15rxd1 k23 i receive data bit 1 p15txd0 m23 o transmit data bit 0 p15txd1 k25 o transmit data bit 1 p15txen l26 i/o* transmit enable (default low) pos reg bit - 19: system will start by itself upon hardware reset system will no t start until bit - 5/6 of register - 16 is set . p16crs_dv g25 i carrier sense/receive data valid p16rxd0 h23 i receive data bit 0 p16rxd1 g26 i receive data bit 1 p16txd0 h26 o transmit data bit 0 p16txd1 j24 o transmit data bit 1 p16txen k24 o transm it enable p17crs_dv f26 i carrier sense/receive data valid p17rxd0 g24 i receive data bit 0 p17rxd1 e25 i receive data bit 1 p17txd0 f25 i/o* transmit data bit 0 (default low) pos reg bit - 4 zbt sram clock timing adjust ment bit - 0 p17txd1 g23 i/o* transmit data bit 1 (default low) pos reg bit - 5 : zbt sram clock timing adjustment bit - 1 p17txen h24 i/o* transmit enable (default low) pos reg bit - 10: reserved p18crs_dv e23 i carrier sense/r eceive data valid p18rxd0 d26 i receive data bit 0 p18rxd1 c25 i receive data bit 1 p18txd0 f24 i/o* transmit data bit 0 (default low) pos reg bit - 6 : zbt sram clock timing adjustment bit - 2 p18txd1 d25 i/o* transmit dat a bit 1 (default low) pos reg bit - 7 : zbt sram clock timing adjustment bit - 3 p18txen e26 i/o* transmit enable pos reg bit - 11 : long event defined as frame longer than 1518/1530 byte (default high) p19crs_dv b24 i carrier sense/receive data valid p19rxd0 a24 i receive data bit 0 p19rxd1 b23 i receive data bit 1 p19txd0 c26 o transmit data bit 0 p19txd1 a25 o transmit data bit 1
page 43 of 77 confidential page 43 43 p19txen d24 o transmit enable p20crs_dv a22 i carrier sense/receive data valid p20rxd0 b21 i receive data bit 0 p20rxd1 c21 i receive data bit 1 p20txd0 b22 i/o* transmit data bit 0 (default low) pos reg bit - 0 zbt sram read timing adjustment bit - 0 p20txd1 d22 i/o* transmit data bit 1 (default low) pos reg b it - 1 : zbt sram read timing adjustment bit - 1 p20txen a23 i/o* transmit enable (default high) pos reg bit - 8 : sram size selection bit - 0 p21crs_dv c20 i carrier sense/receive data valid p21rxd0 d18 i receive dat a bit 0 p21rxd1 a19 i receive data bit 1 p21txd0 b20 i/o* transmit data bit 0 (default low) pos reg bit - 2 zbt sram read timing adjustment bit - 2 p21txd1 a20 i/o* transmit data bit 1 (default low) pos reg bit - 3: zbt sram read timing adjustment bit - 3 p21txen a21 i/o* transmit enable (default low) pos reg bit - 9 : sram size selection bit - 1 p22crs_dv b17 i carrier sense/receive data valid p22rxd0 c18 i receive data bit 0 p22rxd 1 a17 i receive data bit 1 p22txd0 b18 o transmit data bit 0 p22txd1 a18 o transmit data bit 1 p22txen c19 o transmit enable mii interface (port 23) pin name location i/o description p23crs d08 i carrier sense (shar ed with rmii p23crs_dv) p23rxdv b15 i receive data valid p23rxclk a15 i receive clock (25/2.5 mhz) p23rxerr c16 i receive error p23rxd0 a16 i receive data bit 0(shared with rmii p23rxd0) p23rxd1 c17 i receive da ta bit 1(shared with rmii p23rxd1) p23rxd2 b16 i receive data bit 2 p23rxd3 d17 i receive data bit 3 p23col c10 i collision indication p23txen d13 i/o* transmit data valid (shared with rmii p23txen) pos reg bit - 22: rmii tx?s data is driven on falling edge/rising edge (default high). suggest pull - low with 4.7k resister. p23txclk d15 i transmit clock (25/2.5 mhz) p23txd0 c13 i/o* transmit data bit 0 (shared with rmii p23txd0) clkadj reg bit - 0: arl clock ti ming adjustment bit - 0 (default low). p23txd1 d12 i/o* transmit data bit 1(shared with rmii p23txd1) clkadj reg bit - 1: arl clock timing adjustment bit - 1 (default low). p23txd2 c11 i/o* transmit data bit 2 clkadj reg bit - 2: arl clock timing adjustment bit - 2 (default high). p23txd3 d10 i/o* transmit data bit 3 clkadj reg bit - 3: arl clock timing adjustment bit - 3 (default high). phy management interface signals pin name location i/o description m dc ad04 o phy management clock (1.25mhz)
page 44 of 77 confidential page 44 44 mdio ac03 i/o phy management data cpu interface signals name type description uartdi u03 i cpu data input uartdo t03 o cpu data output swirq c06 o cpu interrupt request zbt sram interface pin name location i/o description data00 data01 data02 data03 data04 data05 data06 data07 data08 data09 data10 data11 data12 data13 data14 data15 data1 6 data17 data18 data19 data20 data21 data22 data23 data24 data25 data26 data27 data28 data29 data30 data31 data32 data33 data34 data35 data36 data37 data38 data39 data40 data41 data42 data43 data44 data45 data46 data47 f01 f02 g01 g02 h01 h02 j01 j02 k01 k 02 l01 l02 m01 m02 n01 n02 p01 p02 r01 r02 t01 t02 u01 u02 v01 v02 w01 w02 y01 y02 aa01 aa02 ab01 ab02 ac01 ac02 ad01 ad02 af02 af03 ae03 af04 ae04 af05 ae05 af06 ae06 i/o memory data bus
page 45 of 77 confidential page 45 45 af07 be00 af08 i/o byte enable be01 ae08 i/o byte enable be02 af0 9 i/o byte enable eof ae07 i/o end of frame
page 46 of 77 confidential page 46 46 addr00 addr01 addr02 addr03 addr04 addr05 addr06 addr07 addr08 addr09 addr10 addr11 addr12 addr13 addr14 addr15 addr16 addr17 addr18 b03 b01 c02 c01 d02 d01 e01 e02 b07 a07 a03 b04 a04 b05 a05 b06 a06 b08 a08 o memory address bus nwe c04 o write enable: 0=write 1=read ncs d03 o chip enable, low active arl & mib interfaces signals pin name location i/o description swdir00 swdir01 k03 l03 o data direction indicator : 00 = idle, 01 = receive, 10 = transmit, 11 = control swsync e03 o port synchronization: indicating when port - 0 is driving dat[47:0] swstat00 swstat01 swstat02 swstat03 a14 a13 b13 a12 o data state indicator swstat[3:0]: 0000 ? idle 0001 ? first word (da ) 0010 ? second word (sa) 0011 ? third through last word 0100 ? filter event 0101 ? drop event 0110 ? jabber 0111 ? false carrier (receive) - deferred transmission (transmit) 1000 ? alignment error (receive) - sin gle collision (transmit) 1001 ? flow control (receive) - multiple collision (transmit) 1010 ? short event (receive) - excessive collision (transmit) 1011 ? runt (receive) - late coll ision (transmit) 1100 ? symbol error 1101 ? fcs error 1110 ? long event 1111 ? reserved swrxclk a09 o receive clock, used by acd80800 and acd80900 swtxclk a11 o transmit clock, used by acd80900 only arldi00 arldi01 g04 f03 i arl data input used by acd80800 only: returns 12 - bit arl look - up result to the switch:
page 47 of 77 confidential page 47 47 arldi02 arldi03 h0 3 k04 bit[11:7] - source port id (0 - 23) bit[6:5] ? look - up result: 00 ? reserved 01 ? matched 10 ? not matched 11 ? forced discard bit[4:0] - destination port id (0 - 23) arldiv j04 i arl data input valid: assertion to indicate start of a new result on arldi[3:0]. used by acd80900 only. led interface signals pin name location i/o description ledvld 0 w03 i/o* led signal valid #0 (default low) pos reg bit - 13: internal arl selected (2k mac address entry)/ external arl selected (11k mac address entry). ledvld1 y04 i/o* led signal valid #1 (default low) pos reg bit - 14: phy ids start from 0 or 1 ledclk v03 i/o* 2.5 mhz led clock pos reg bit - 12: frames with unknown da forwarded to the dumping port or all ports (default low). nled0 r04 i/o* when ledvld1 is high, it's frame error indicator. pos reg bit - 18: system e rrors will trigger software/hardware reset. (default low) nled1 r03 i/o* when ledvld1 is high, it's full duplex indication. when ledvld1 is high, it's collision indication. pos reg bit - 17: flow control on broadcast queue utilization enable/disable. (defa ult low) nled2 n03 i/o* when ledvld0 is high, it's speed (1:10mbps, 0: 100mbps). when ledvld1 is high, it's receiving activity. pos reg bit - 16: automatic phy management enabled/disabled. (default low) nled3 p04 i/o* when ledvld0 is high, it' s link status. when ledvld0 is high, it's transmit activity. pos reg bit - 15: re - transmit after excessive collision/drop after excessive collision. (default low) system control interface signals pin name location i/o description clk100 ab04 i 100 mhz main clock input wchdog y03 o watch dog life pulse. 2.5mhz continuous clock. syserror m03 o system error indication high active. when there is any error occurs in syserr reg, it?s asserted to high. nreset ab03 i h ardware reset, low active testen d07 i factory used only. connect to ground. clksel d20 i factory used only. connect to ground. en16p ac05 i factory used only. connect to ground. zbtclk p03 o factory used only. not connect
page 48 of 77 confidential page 48 48 table - 8.1a: pin list sorted by location ( 1 of 3 ) location pin name i/o pos location pin name i/o pos a01 vss c14 vddq a02 vss c15 vdd a03 addr10 o c16 p23rxer i a04 addr12 o c17 p23rxd1 i a05 addr14 o c18 p22rxd0 i a06 addr16 o c19 p22txen o a07 addr09 o c20 p21crs_dv i a08 addr18 o c21 p20rxd1 i a09 swrxclk o c22 vddq a10 pid2 o c23 miiclk5 o a11 swtxclk o c24 vss a12 stat3 o c25 p18rxd1 i a13 stat1 o c26 p19txd0 o a14 stat0 o d01 addr05 o a15 p23rxclk i d02 addr04 o a16 p23rxd0 i d03 ncs o a17 p22rxd1 i d04 vss a18 p22txd1 o d05 vddq a19 p21rxd1 i d06 vddq a20 p21txd1 i/o 3 d07 testen i a21 p21txen i/o 9 d08 p23crs i a22 p20crs_dv i d09 vss a23 p20txen i/o 8 d10 p23txd3 i/o 28 a24 p19rxd0 i d 11 vddq a25 p19txd1 o d12 p23txd1 i/o 26 a26 vss d13 p23txen i/o 22 b01 addr01 o d14 vss b02 vss d15 p23txclk o b03 addr00 o d16 vddq b04 addr11 o d17 p23rxd3 i b05 addr13 o d18 p21rxd0 i b06 addr15 o d19 vss b07 addr08 o d20 clksel i b08 addr17 o d21 vddq b09 pid4 o d22 p20txd1 i/o 1 b10 pid3 o d23 vss b11 pid1 o d24 p19txen o b12 pid0 o d25 p18txd1 i/o 7 b13 stat2 o d26 p18rxd0 i b14 vddq e01 addr06 o b15 p23rxdv i e02 addr07 o b16 p23rxd2 i e03 s wsync o b17 p22crs_dv i e04 vddq b18 p22txd0 o e23 p18crs_dv i b19 vdd e24 vdd b20 p21txd0 i/o 2 e25 p17rxd1 i b21 p20rxd0 i e26 p18txen i/o 11 b22 p20txd0 i/o 0 f01 data00 i/o b23 p19rxd1 i f02 data01 i/o b24 p19crs_dv i f03 arldi1 i b25 vss f04 vddq b26 vss f23 vddq c01 addr03 o f24 p18txd0 i/o 6 c02 addr02 o f25 p17txd0 i/o 4 c03 vss f26 p17crs_dv i c04 new o g01 data02 i/o c05 vdd g02 data03 i/o c06 swirq o g03 vdd c07 vddq g04 arldi0 i c08 vddq g23 p17txd1 i/o 5 c09 vdd g24 p17rxd0 i c10 p23col i g25 p16crs_dv i c11 p23txd2 i/o 27 g26 p16rxd1 i c12 vddq h01 data04 i/o c13 p23txd0 i/o 25 h02 data05 i/o table - 8.1b: pin list sorted by location ( 2 of 3 )
page 49 of 77 confidential page 49 49 location pin n ame i/o pos location pin name i/o pos h03 arldi2 i p02 data17 i/o h04 vss p03 zbtclk o h23 p16rxd0 i p04 nled3 i/o 15 h24 p17txen i/o 10 p11 vss h25 vddq p12 vss h26 p16txd0 o p13 vss j01 data06 i/o p14 vss j02 data07 i/o p15 vss j03 vddq p16 vss j04 arldiv i p23 vss j23 vss p24 p14txen i/o 21 j24 p16txd1 o p25 p13txen o j25 miiclk4 o p26 p13txd1 o j26 vdd r01 data18 i/o k01 data08 i/o r02 data19 i/o k02 data09 i/o r03 nled1 i/o 17 k03 swdir0 o r04 n led0 i/o 18 k04 arldi3 i r11 vss k23 p15rxd1 i r12 vss k24 p16txen o r13 vss k25 p15txd1 o r14 vss k26 p15rxd0 i r15 vss l01 data10 i/o r16 vss l02 data11 i/o r23 p13txd0 o l03 swdir1 o r24 p13crs_dv i l04 vddq r25 p12rxd0 i l11 vss r26 p12rxd1 i l12 vss t01 data20 i/o l13 vss t02 data21 i/o l14 vss t03 uartdo o l15 vss t04 vddq l16 vss t11 vss l23 vddq t12 vss l24 p15crs_dv i t13 vss l25 p14rxd0 i t14 vss l26 p15txen i/o 19 t15 vss m01 data12 i/o t16 vss m02 data13 i/o t23 vddq m03 syserr o t24 vddq m04 vdd t25 p12txd1 o m11 vss t26 vdd m12 vss u01 data22 i/o m13 vss u02 data23 i/o m14 vss u03 uartdi i m15 vss u04 vdd m16 vss u23 p12txd0 o m23 p15txd0 o u24 p12crs_dv i m24 p14rxd1 i u25 p11rxd1 i m25 p14txd0 o u26 p12txen i/o 20 m26 p14crs_dv i v01 data24 i/o n01 data14 i/o v02 data25 i/o n02 data15 i/o v03 nledclk i/o 12 n03 nled2 i/o 16 v04 vss n04 vss v23 p11txen i/o 23 n11 vss v24 miiclk3 o n12 vss v25 p11crs_dv i n13 vss v26 p11rxd0 i n14 vss w01 data26 i/o n15 vss w02 data27 i/o n16 vss w03 ledvld0 i/o 13 n23 p13rxd0 i w04 vddq n24 p14txd1 o w23 vss n25 vdd w24 p11txd1 o n26 p13rx d1 i w25 p10rxd1 i p01 data16 i/o w26 p11txd0 o
page 50 of 77 confidential page 50 50 table - 8.1c: pin list sorted by location ( 3 of 3 ) location pin name i/o pos location pin name i/o pos y01 data28 i/o ad16 p04txd0 o y02 data29 i/o ad17 p04rxd1 i y03 wchdog o ad18 p05crs_dv i y04 ledvld1 i/o 14 ad19 p06txd0 o y23 p09rxd1 i ad20 p06rxd0 i y24 p10rxd0 i ad21 p07txd0 o y25 p10txd1 o ad22 p07rxd1 i y26 p10crs_dv i ad23 p08txen i/o 31 aa01 data30 i/o ad24 vss aa02 data31 i/o ad25 p08crs_dv i aa03 v dd ad26 p08rxd0 i aa04 vddq ae01 vss aa23 vddq ae02 vss aa24 p10txen o ae03 data40 i/o aa25 vdd ae04 data42 i/o aa26 p10txd0 o ae05 data44 i/o ab01 data32 i/o ae06 data46 i/o ab02 data33 i/o ae07 eof i/o ab03 nreset i ae08 be 1 i/o ab04 clk100 i ae09 vddq ab23 p09crs_dv i ae10 p00crs_dv i ab24 p09rxd0 i ae11 p01txen o ab25 p09txd1 o ae12 p01crs_dv i ab26 vddq ae13 p02txen i/o 42 ac01 data34 i/o ae14 p02rxd0 i ac02 data35 i/o ae15 p03txd1 i/o 38 ac03 mdio i/o ae16 p03rxd0 i ac04 vss ae17 vddq ac05 en16p i ae18 p04rxd0 i ac06 vddq ae19 p05txd0 i/o 39 ac07 miiclk0 o ae20 p05rxd0 i ac08 vss ae21 p06txd1 o ac09 p00txd0 i/o 33 ae22 p06rxd1 i ac10 p00rxd1 i ae23 p07txd1 o ac 11 vddq ae24 miiclk2 o ac12 p02txd0 i/o 35 ae25 vss ac13 vss ae26 p08txd1 o ac14 p02rxd1 i af01 vss ac15 p04txen o af02 data38 i/o ac16 vddq af03 data39 i/o ac17 p04crs_dv i af04 data41 i/o ac18 vss af05 data43 i/o ac19 p05rxd1 i af06 data45 i/o ac20 vdd af07 data47 i/o ac21 vddq af08 be0 i/o ac22 p07crs_dv i af09 be2 i/o ac23 vss af10 p00rxd0 i ac24 p09txen i/o 32 af11 p01txd1 o ac25 p08rxd1 i af12 p01rxd0 i ac26 p09txd0 o af13 p02txd1 i/o 36 ad01 data3 6 i/o af14 p03txen i/o 24 ad02 data37 i/o af15 vdd ad03 vss af16 miiclk1 o ad04 mdc o af17 p04txd1 o ad05 vdd af18 p05txen i/o 29 ad06 vddq af19 p05txd1 i/o 40 ad07 p00txen i/o 41 af20 p06txen i/o 30 ad08 p00txd1 i/o 34 af21 p06crs_dv i ad09 vdd af22 p07txen o ad10 p01txd0 o af23 p07rxd0 i ad11 p01rxd1 i af24 p08txd0 o ad12 p02crs_dv i af25 vss ad13 p03txd0 i/o 37 af26 vss ad14 p03crs_dv i ad15 p03rxd1 i
page 51 of 77 confidential page 51 51 table - 8.2a: pin list sorted by name ( 1 o f 3 ) pin name i/o pos location pin name i/o pos location addr00 o b03 data36 i/o ad01 addr01 o b01 data37 i/o ad02 addr02 o c02 data38 i/o af02 addr03 o c01 data39 i/o af03 addr04 o d02 data40 i/o ae03 addr05 o d01 data41 i/o af04 addr0 6 o e01 data42 i/o ae04 addr07 o e02 data43 i/o af05 addr08 o b07 data44 i/o ae05 addr09 o a07 data45 i/o af06 addr10 o a03 data46 i/o ae06 addr11 o b04 data47 i/o af07 addr12 o a04 en16p i ac05 addr13 o b05 eof i/o ae07 addr14 o a 05 ledvld0 i/o 13 w03 addr15 o b06 ledvld1 i/o 14 y04 addr16 o a06 mdc o ad04 addr17 o b08 mdio i/o ac03 addr18 o a08 miiclk0 o ac07 arldi0 i g04 miiclk1 o af16 arldi1 i f03 miiclk2 o ae24 arldi2 i h03 miiclk3 o v24 arldi3 i k04 miiclk4 o j25 arldiv i j04 miiclk5 o c23 clksel i d20 ncs o d03 be0 i/o af08 nled0 i/o 18 r04 be1 i/o ae08 nled1 i/o 17 r03 be2 i/o af09 nled2 i/o 16 n03 clk100 i ab04 nled3 i/o 15 p04 data00 i/o f01 nledclk i/o 12 v03 data01 i/o f02 nreset i ab03 data02 i/o g01 nwe o c04 data03 i/o g02 p00crs_dv i ae10 data04 i/o h01 p00rxd0 i af10 data05 i/o h02 p00rxd1 i ac10 data06 i/o j01 p00txd0 i/o 33 ac09 data07 i/o j02 p00txd1 i/o 44 ad08 data08 i/o k01 p00txen i/o 41 a d07 data09 i/o k02 p01crs_dv i ae12 data10 i/o l01 p01rxd0 i af12 data11 i/o l02 p01rxd1 i ad11 data12 i/o m01 p01txd0 o ad10 data13 i/o m02 p01txd1 o af11 data14 i/o n01 p01txen o ae11 data15 i/o n02 p02crs_dv i ad12 data16 i/o p01 p02rxd0 i ae14 data17 i/o p02 p02rxd1 i ac14 data18 i/o r01 p02txd0 i/o 35 ac12 data19 i/o r02 p02txd1 i/o 36 af13 data20 i/o t01 p02txen i/o 42 ae13 data21 i/o t02 p03crs_dv i ad14 data22 i/o u01 p03rxd0 i ae16 data23 i/o u02 p03rxd1 i ad15 data24 i/o v01 p03txd0 i/o 37 ad13 data25 i/o v02 p03txd1 i/o 38 ae15 data26 i/o w01 p03txen i/o 24 af14 data27 i/o w02 p04crs_dv i ac17 data28 i/o y01 p04rxd0 i ae18 data29 i/o y02 p04rxd1 i ad17 data30 i/o aa01 p04txd0 o ad16 data 31 i/o aa02 p04txd1 o af17 data32 i/o ab01 p04txen o ac15 data33 i/o ab02 p05crs_dv i ad18 data34 i/o ac01 p05rxd0 i ae20 data35 i/o ac02 p05rxd1 i ac19
page 52 of 77 confidential page 52 52 table - 8.2b: pin list sorted by name ( 2 of 3 ) pin name i/o pos location pi n name i/o pos location p05txd0 i/o 39 ae19 p16rxd1 i g26 p05txd1 i/o 40 af19 p16txd0 o h26 p05txen i/o 29 af18 p16txd1 o j24 p06crs_dv i af21 p16txen o k24 p06rxd0 i ad20 p17crs_dv i f26 p06rxd1 i ae22 p17rxd0 i g24 p06txd0 o ad19 p17rxd1 i e25 p06txd1 o ae21 p17txd0 i/o 4 f25 p06txen i/o 30 af20 p17txd1 i/o 5 g23 p07crs_dv i ac22 p17txen i/o 10 h24 p07rxd0 i af23 p18crs_dv i e23 p07rxd1 i ad22 p18rxd0 i d26 p07txd0 o ad21 p18rxd1 i c25 p07txd1 o ae23 p18txd0 i/o 6 f24 p0 7txen o af22 p18txd1 i/o 7 d25 p08crs_dv i ad25 p18txen i/o 11 e26 p08rxd0 i ad26 p19crs_dv i b24 p08rxd1 i ac25 p19rxd0 i a24 p08txd0 o af24 p19rxd1 i b23 p08txd1 o ae26 p19txd0 o c26 p08txen i/o 31 ad23 p19txd1 o a25 p09crs_dv i ab23 p 19txen o d24 p09rxd0 i ab24 p20crs_dv i a22 p09rxd1 i y23 p20rxd0 i b21 p09txd0 o ac26 p20rxd1 i c21 p09txd1 o ab25 p20txd0 i/o 0 b22 p09txen i/o 32 ac24 p20txd1 i/o 1 d22 p10crs_dv i y26 p20txen i/o 8 a23 p10rxd0 i y24 p21crs_dv i c20 p 10rxd1 i w25 p21rxd0 i d18 p10txd0 o aa26 p21rxd1 i a19 p10txd1 o y25 p21txd0 i/o 2 b20 p10txen o aa24 p21txd1 i/o 3 a20 p11crs_dv i v25 p21txen i/o 9 a21 p11rxd0 i v26 p22crs_dv i b17 p11rxd1 i u25 p22rxd0 i c18 p11txd0 o w26 p22rxd1 i a17 p11txd1 o w24 p22txd0 o b18 p11txen i/o 23 v23 p22txd1 o a18 p12crs_dv i u24 p22txen o c19 p12rxd0 i r25 p23col i c10 p12rxd1 i r26 p23crs - dv/crs i d08 p12txd0 o u23 p23rxclk i a15 p12txd1 o t25 p23rxd0 i a16 p12txen i/o 20 u26 p2 3rxd1 i c17 p13crs_dv i r24 p23rxd2 i b16 p13rxd0 i n23 p23rxd3 i d17 p13rxd1 i n26 p23rxdv i b15 p13txd0 o r23 p23rxer i c16 p13txd1 o p26 p23txclk o d15 p13txen o p25 p23txd0 i/o 25 c13 p14crs_dv i m26 p23txd1 i/o 26 d12 p14rxd0 i l 25 p23txd2 i/o 27 c11 p14rxd1 i m24 p23txd3 i/o 28 d10 p14txd0 o m25 p23txen i/o 22 d13 p14txd1 o n24 pid0 o b12 p14txen i/o 21 p24 pid1 o b11 p15crs_dv i l24 pid2 o a10 p15rxd0 i k26 pid3 o b10 p15rxd1 i k23 pid4 o b09 p15txd0 o m23 st at0 o a14 p15txd1 o k25 stat1 o a13 p15txen i/o 19 l26 stat2 o b13 p16crs_dv i g25 stat3 o a12 p16rxd0 i h23 swdir0 o k03
page 53 of 77 confidential page 53 53 table - 8.2c: pin list sorted by name ( 3 of 3 ) pin name i/o pos location pin name i/o pos location swirq o c06 vss ac23 swrxclk o a09 vss ad03 swsync o e03 vss ad24 swtxclk o a11 vss ae01 syserr o m03 vss ae02 testen i d07 vss ae25 uartdi i u03 vss af01 uartdo o t03 vss af25 vdd aa03 vss af26 vdd aa25 vss b02 vdd ac20 vss b25 vdd ad05 vss b26 vdd ad09 vss c03 vdd af15 vss c24 vdd b19 vss d04 vdd c05 vss d09 vdd c09 vss d14 vdd c15 vss d19 vdd e24 vss d23 vdd g03 vss h04 vdd j26 vss j23 vdd m04 vss l11 vdd n25 v ss l12 vdd t26 vss l13 vdd u04 vss l14 vddq aa04 vss l15 vddq aa23 vss l16 vddq ab26 vss m11 vddq ac06 vss m12 vddq ac11 vss m13 vddq ac16 vss m14 vddq ac21 vss m15 vddq ad06 vss m16 vddq ae09 vss n0 4 vddq ae17 vss n11 vddq b14 vss n12 vddq c07 vss n13 vddq c08 vss n14 vddq c12 vss n15 vddq c14 vss n16 vddq c22 vss p11 vddq d05 vss p12 vddq d06 vss p13 vddq d11 vss p14 vddq d16 vss p15 vddq d21 vss p16 vddq e04 vss p23 vddq f04 vss r11 vddq f23 vss r12 vddq h25 vss r13 vddq j03 vss r14 vddq l04 vss r15 vddq l23 vss r16 zbtclk o p03 vss t11 vddq t04 vss t12 vddq t23 vss t13 vddq t24 vss t14 vddq w04 vss t15 vss a01 vss t16 vss a02 vss v04 vss a26 vss w23 vss ac04 wchdog o y03 vss ac08 vss ac13
page 54 of 77 confidential page 54 54 9. timing description figure - 9.1a rmii receive timing figure - 9.1b: rmii transmit timing t1 t2 rfe_clk rxd[1:0] t# description: min typ max unit t1 rxdv, rxd setup time 4 - - ns t2 rxdv, rxd hold time 2 - - ns ref_clk txd[1:0] t1 t# desciption min typ max unit t1 txen, txd setup time 4 - - ns t2 txen, txd hold time 2 - - ns t2
page 55 of 77 confidential page 55 55 figure - 9.2a mii receive timing figure - 9.2b: mii transmit timing txclk txen txd[3:0] t2 t1 t# desciption min typ max unit t1 txen, txd setup time 10 - - ns t2 txen, txd hold time 10 - - ns t1 t2 rxclk rxdv rxd[3:0] rxer t# description: min typ max unit t1 rx_dv, rxd, rx_er setup time 5 - - ns t2 rx_dv, rxd, rx_er hold time 5 - - ns
page 56 of 77 confidential page 56 56 figure - 9.3: phy management read timing figure - 9.4: phy management write timing t1 mdc mdio t2 t# description min typ max unit t1 mdio setup time 0 - 300 ns t2 mdc cycle - 800 - ns t1 t2 mdc mdio t3 t4 t5 t# description min typ max unit t1 mdc high time 360 - 440 ns t2 mdc low time 360 - 440 ns t3 mdc period - 800 - ns t4 mdio set up time 10 - - ns t5 mdio hold time 10 - - ns
page 57 of 77 confidential page 57 57 figure - 9.5: sram (zbt ) read/write timing address data nwe nce t4 mclk t6 t1 t2 t3 t8 t9 t11 t5 t7 a1 a2 a3 q1 q2 d3 d4 a4 t13 t12 t15 t14 t10 t# description: min max unit t1 clock cycle time 10 - ns t2 clock high time 4 - ns t3 clock low time 4 - ns t4 chip enable setup time 3 - ns t5 chip enable hold time 2 - ns t6 read/write setup time 3 - ns t7 read/write hold time 2 - ns t8 address setup time 3 - ns t9 address hold time 2 - ns t10 clock to output data in low-z 1.5 - ns t11 clock to output data valid - 5 ns t12 clock to output data invalid 1.5 - ns t13 clock to output data in high-z - 4 ns t14 input data setup time 3 - ns t15 input data hold time 1 - ns
page 58 of 77 confidential page 58 58 figure - 9.6: cpu command timing figure - 9.7: arl result timing t# description min typ max unit t1 cpu idle time 0 - - us t2 cpu command bit time 10 - 1000 us t3 response time 0 - 20 ms t4 command time - - 20 ms t2 cpudi idle state start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 stop bit t1 cpudo stop bit start bit stop bit t3 bit 7 bit 6 bit0 t4 t2 t3 da1 result1 da2 arlclk arldo arldi t1 result2 t# description min typ max unit t1 time between das 0 - - ns t2 time for arl result 0 - 200 ns t3 time between results 0 - - ns
page 59 of 77 confidential page 59 59 figure - 9.8: led signal timing nled0 nled1 nled3 nled2 ledclk p23 p22 p21 p2 p1 p0 p23 p22 p21 p2 p1 p0 ledvld0 ledvld1 fd x sp d lnk fd x sp d lnk fd x sp d lnk fd x sp d lnk fd x sp d lnk fd x sp d lnk er r co l rc v xm t er r co l rc v xm t er r co l rc v xm t er r co l rc v xm t er r co l rc v xm t er r co l rc v xm t * p[7:0] time slots is not used for 82216
page 60 of 77 confidential page 60 60 10. electrical specification 10. electrical specification figure - 10.1: absolute maximum ratings item symbol rating dc supply voltage for core vdd 3.0 v dc supply voltage for i/o vddq 4.0 v input signal voltage v in 3.6 v signal current i i/o 2.5ma dc ou t pu t voltage vo 2.8v figure - 10.2 recommended operation conditions item symbol rating dc supply voltage for c ore vdd 2.5v dc supply voltage for i/o vddq 3.3v operating temperature t a 0 ? 70 c maximum power consumption n/a tbd
page 61 of 77 confidential page 61 61 11. packaging side view 0.6 2.33 0.56 bottom view 31.75 0.75 0.635 1.27 2 4 6 8 10 12 14 16 18 20 22 24 26 aa ab ac ad ae af a b c d e f g h j k l m n p r t u v w y 11 13 15 17 19 21 23 25 1 3 5 7 9 top view 30 35 advanced comm. devices flllll smayyww acd822xx
page 62 of 77 confidential page 62 62 appendix - a1 address resolution logic built - in arl with 2048 mac addres ses
page 63 of 77 confidential page 63 63 1. summary the internal address resolution logic (arl) of the switch controllers automatically builds up an address table and maps up to 2,048 mac addresses for the associated ports. cpu intervention is not required in an un - managed system. for a mana ged system, the management cpu can configure the operation mode of the arl, learn all the addresses in the address table, add new addresses into the lookup table, control security or filtering feature of each address entry etc. the arl high performance de sign guarantee very low latency and will never slow down the frame switching operation. it helps the switch controllers maintain wire speed forwarding rate under any type of traffic load. the 2k internal addresses space can be expanded to 11k entries by u sing the external arl, acd80800. figure - 1: built - in arl block diagram external cpu interface address registers data registers command registers control registers internal switch interface address learning engine cpu interface engine address table (2048 entries) address aging engine address lookup engine
page 64 of 77 confidential page 64 64 2. features supports up to 2,048 internal mac address lookup provides uart type of interface for management cpu wire speed address lookup time. wire speed address learning time. ad dress can be automatically learned from switch without external cpu intervention address can be manually added by the cpu through cpu interface each mac address can be secured by the cpu from being changed or aged out each mac address can be marked by the cpu from receiving any frame each newly learned mac address is notified to the cpu each aged out mac address is notified to the cpu automatic address aging control, with configurable aging period 3. functional description the internal arl provides addr ess resolution service for the switch controllers. figure - 1 is a block diagram of the arl. traffic snooping all ethernet frames received by the switch controller have to be stored into memory buffer. as the frame data are written into memory. the statu s of the data shown on the data bus is displayed by the switch controller through the swstat[3:0] bus. the arl interface with the switch controller contains the signals of the data bus and the state bus. by snoop the data bus and the state bus of the switc h controller, the internal arl can detect destination mac address and source mac address embedded inside each frame. address learning each source mac address extracted from the data bus, along with the ingress port id, is passed to the address learning engine of the arl. 1. the address learning engine first determines whether the frame is a valid frame. 2. for a valid frame, it will first try to find the source address from the current address table. 3. if that address is not listed, or the port id associated with the listed mac address does not match the ingress port id, it will be learned into the address table as a new address. 4. after an address is learned by the address learning engine, the cpu can be notified to read this newly learned address so that it c an add it into the cpu?s address table. 5. if the address table is full, address learning engine will not learn any the new mac address unless there is new entry available (i.e. address aging - out). address aging after each source address is learned into the address table, it has to be refreshed at least once within each address aging period. refresh means it is caught again from the switch interface. if it has not occurred for a pre - set aging period, the a ddress aging engine will remove the address from t he address table. after an address is removed by the address aging engine, the cpu can be notified through interrupt request that it needs to read this aged out address so that it can remove this address from the cpu?s address table.
page 65 of 77 confidential page 65 65 the default aging t ime is 300 seconds. that means a ddress aging engine checks the timer every 300 seconds from power up. if the new address is learned just after the aging - out checking process finished. the worst case aging time can be about 600 seconds. you can program the timer register through cpu interface (uart). the register is resided in register18 and 19 of arl. address lookup each destination address is passed to the address lookup engine of the arl. the address lookup engine checks if the destination address ma tches with any existing address in the address table. if it does, the arl returns the associated port id to switch controller. otherwise, a ?no match? result is passed to switch controller. cpu interface the cpu can access the registers of the arl by s ending commands to the uart data input line. each command is consists of action (read or write), register type, register index, and data. each result of command execution is returned to the cpu through the uart data output line. registers the arl pr ovides a number of registers for the control cpu. through these registers, the cpu can read all address entries of the address table, delete particular addresses from the table, add particular addresses into the table, secure an address from being changed, set filtering on some addresses, change the hashing algorithm etc. through interrupt request signals, the cpu can be notified whenever it needs to retrieve data for a newly - learned address or an aged - out address so that the cpu can build an exact same add ress table learned by the arl. cpu interface engine the command sent by the control cpu is executed by the cpu interface engine. for example, the cpu may send a command to learn the first newly learned address. the cpu interface engine is responsible to find the newly learned address from the address table, and passes it to the cpu. the cpu may request to learn next newly learned address. and the cpu interface engine starts to search for next newly learned address from the address table. address table the address table can hold up to 2,048 mac addresses, together with the associated port id, security flag, filtering flag, new flag, aging information etc. the address table resides in the embedded sram inside the built - in arl.
page 66 of 77 confidential page 66 66 4. interface description cpu interface the cpu can communicate with the arl through the uart interface of the switch controller. the management cpu can send commands to the arl by writing into associated registers, and retrieve result from the arl by reading out of the correspo nding registers. the registers are described in the section on ?register description.? the cpu interface signals are described by table - 1 : table - 1: cpu interface name i/o description uartdi i uart input data line. uartdo o uart output data line. uartd i is used by the control cpu to send commands into the arl. the baud rate will be automatically detected by the arl. the result is returned through the uartdo line with the detected baud rate. the format of the command packet is shown as follows: a comman d sent by the cpu through the cpudi line consists of 7 octets. command frames transmitted on cpudi have the format shown below: arl cpudi format operation command address data checksum write 0100xx11 a[7:0] d[31:0] c[7:0] read 0100xx01 a[7:0 ] d[31:0] c[7:0] the byte order of data in all fields follows the big - endian convention, i.e. most significant octet first. the bit order is the least significant order first. the command octet specifies the type of the operation. the bit - 7, bit - 6, and bit - 5 of the command octet are specified the device type. (1) switch controller, the device type is 001. (2) arl controller, the device type is 010. (3) management controller, the device type is 100. the bit - 2, and bit - 3 of the command octet are used to specify t he device id of the chip which is shared with ACD82224 device id (ACD82224 bit 20 and bit 21 of register 25). the address octet specifies the number of the register. for write operation, the data field is a 4 - octet value to specify what to w rite into the register. for read operation, the data field is a 4 - octet 0 as padded data. if the data of register is less than 32 - bit, it is align to bit - 0 of data field. the checksum value is an 8 - bit value of exclusive - or of all octets in the frame, st arting from the command octet. for each valid command received, the arl will always send a response. response from the arl is sent through the cpudo line. response frames sent by the ACD82224 have the following format: arl uartdo (response) format respon se command address data checksum write 0100xx11 a[7:0] d[31:0] c[7:0]
page 67 of 77 confidential page 67 67 read 0100xx01 a[7:0] d[31:0] c[7:0] for response to a read operation, the data field is a 4 - octet value to indicate the content of the register. for response to a write operation, th e data field is 32 bits of 0. if the data of register is less than 24 - bit, it is align to bit - 0 of data field. the checksum value is an 8 - bit value of exclusive - or of all octets in the response frame, starting from the command octet. the arl will always check the command header to see if both the device type and the device id matches with its setting. if not, it ignores the command and does not generate any response to this command. 5. register description the built - in arl provides a number of regis ters for the cpu to access the address table. commands are sent to arl by writing into the associated registers. before the cpu can pass a command to arl, it must check the result register (register - 11) for execution status of the previous command. the cpu may need to retrieve the previous result before sending new command. then the cpu will write the new command parameters into the data registers, and the command type into the command register. the arl will then reset the result register to 0. the result r egister will indicate the completion of the command at the end of the execution. before the completion of the execution, any command written into the command register is ignored by the arl. the registers accessible to the cpu are described by table - 2 : t able - 2: register description reg. register name type size description 0 datareg0 r/w 8 bit byte 0 of data 1 datareg1 r/w 8 bit byte 1 of data 2 datareg2 r/w 8 bit byte 2 of data 3 datareg3 r/w 8 bit byte 3 of data 4 datareg4 r/w 8 bit byte 4 of data 5 datareg5 r/w 8 bit byte 5 of data 6 datareg6 r/w 8 bit byte 6 of data 7 datareg7 r/w 8 bit byte 7 of data 8 addrreg0 r/w 8 bit lsb of address value 9 addrreg1 r/w 8 bit msb of address value 10 cmdreg r/w 8 bit command register 11 rsltreg r/w 5 bit result register 12 cfgreg r/w 8 bit configuration register 13 intsrcreg r/w 8 bit interrupt source register 14 intmskreg r/w 8 bit interrupt mask register 15 nlearnreg0 r/w 8 bit address learning disable register for port 0 ? 7 16 nlearnreg1 r/w 8 bit address learning disable register for port 8 ? 15 17 nlearnreg2 r/w 8 bit address learning disable register for port 16 ? 23 18 agetimereg0 r/w 8 bit lsb of aging period register 19 agetimereg1 r/w 8 bit msb of aging period register 20 poscfg r/w 3 bi t power on strobe configuration register
page 68 of 77 confidential page 68 68 datareg0 ~ datareg7 (register 0 ~ register 7) the datareg[0:7] are registers used to pass the command parameters to the arl, and the execution results to the cpu. arl only stores 47 - bit of mac address, the firs t bit of the first byte (msb) is not stored in arl table (this bit to indicate broadcast/multicast frame). the data in data register 0 is shift left one bit compared to the mac msb. for example, if the mac address is ?08 - 00 - 12 - 34 - 56 - 78?, datareg - 0 is store d the value of ?04? instead of ?08?. addrreg0 and addrreg1 (register 8 and register 9) the addrreg[0:1] are used to specify the address associated with the command. cmdreg (register 10) the cmdreg is used to pass the type of command to the arl. the c ommand types are listed in table - 3 . the details of each command are described in the chapter of ?command description.? table - 3: command list command description 0x09 add the specified mac address into the address table 0x0a set a lock for the specified mac address 0x0b set a filtering flag for the specified mac address 0x0c delete the specified mac address from the address table 0x0d assign a port id to the specified mac address 0x10 read the first entry of the address table 0x11 read next entry of address book 0x20 read first valid entry 0x21 read next valid entry 0x30 read first new entry 0x31 read next new entry 0x40 read first aged entry 0x41 read next aged entry 0x50 read first locked entry 0x51 read next locked entry 0x60 read first f iltered entry 0x61 read next filtered entry 0x80 read first entry with specified pid 0x81 read next entry with specified pid 0xff arl reset
page 69 of 77 confidential page 69 69 rstreg (register 11) the rstreg is used to indicate the status of command execution. the result co de is listed as follows: bit description default 3:0 4 - bit error code 0000 ? no error 0001 ? cannot find the specified entry other ? errors 0000 4 command completed. 0 ? e xecution has been started but not yet completed 1 ? e xecution has been complete d, must check bit[3:0], any error occurring. 0 cfgreg (register 12) the cfgreg is used to configure the arl functions. the bit definition of cfgreg is described as: bit description default 0 disable address aging 0 1 disable address lookup 0 2 na 0 3 na 0 7:4 hashing algorithm selection 0000 intsrcreg (register 13) the intsrcreg is used to indicate what can cause interrupt request to cpu. the source of interrupt is listed as: bit description default 0 aged address exists 0 1 new address exis ts 0 2 reserved 0 3 reserved 0 4 bucket overflowed 0 5 command is done 1 6 system initialization is completed 1 7 self test failure 0 intmskreg (register 14) the intmskreg is used to enable an interrupt source to generate an interrupt request. the bit definition is the same as intsrcreg. a 1 in a bit enables the corresponding interrupt source to generate an interrupt request once it is set. bit description default
page 70 of 77 confidential page 70 70 0 aged address exists 1 1 new address exists 1 2 reserved 1 3 reserved 1 4 buck et overflowed 1 5 command is done 1 6 system initialization is completed 1 7 self test failure 1 nlearnreg0 ~ nlearnreg2 (register 15 ~ register 17) the nlearnreg[2:0] are used to disable address learning activity from a particular port. if the bit corresponding to a port is set, the arl will not try to learn new addresses from that port. the nlearnreg0/1/2 are bit - to - port mapping registers. the bit[0:7] of nlearnreg0 is represented by port[0:7]. the bit[0:7] of nlearnreg1 is represented by port[8 :15]. the bit[0:7] of nlearnreg2 is represented by port[16:23]. agetimereg0 and agetimereg1 (register 18 and register 19) the agetimereg[1:0] are used to specify the period of address aging control. the aging period can be from 0 to 65535 units, with each unit counted as 2.684 second. the default age time is 300 seconds. to make the new setting age period effective, cpu must send ?arl reset? (0xff, see arl table - 3) command to arl after configuring the new agetimereg[1:0] and set the bit - 0 of register - 20 to one to wake up arl engine poscfgreg (register 20) the poscfgreg is a configuration register whose default value is determined by the pull - up or pull - down status of the associated hardware pin. the bits of poscfgreg0 is listed as follows: bit des cription default shared pin 0 reserved 0 na 1 nocpu 0 ? wait for cpu 1 ? arl initializes by itself 0 p00txen 2 reserved 0 p02txen note: if nocpu is set to 0, the arl will not start the initialization process until bit - 1 of poscfgreg is set to 1. 6 . command description command 09h description: add the specified mac address into the address table.
page 71 of 77 confidential page 71 71 parameter: store the mac address into datareg5 ? datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. store the as sociated port number into datareg6. result: the mac address will be stored into the address table if there is space available. the result is indicated by the result register. command 0ah description: set the lock bit for the specified mac address. pa rameter: store the mac address into datareg5 ? datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. result: the state machine will seek for an entry with matched mac address, and set the lock bit of the entry. the re sult is indicated by the result register. command 0bh description: set the filter flag for the specified mac address. parameter: store the mac address into datareg5 ? datareg0, with datareg5 contains the msb of the mac address and datareg0 contains th e lsb. result: the state machine will seek for an entry with matched mac address, and set the filter bit of the entry. the result is indicated by the result register. command 0ch description: delete the specified mac address from the address table. parameter: store the mac address into datareg5 ? datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. result: the mac address will be removed from the address table. the result is indicated by the result register. command 0dh description: assign the associated port number to the specified mac address. parameter: store the mac address into datareg5 ? datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. store the port number in to datareg6. result: the port id field of the entry containing the specified mac address will be changed accordingly. the result is indicated by the result register. command 10h description: read the first entry of the address table. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of the first entry of the address book will be stored into the data registers. the mac
page 72 of 77 confidential page 72 72 address will be stored into datareg5 ? datareg0, with dat areg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag * bits are stored in datareg7.the read pointer will be set to point to second entry of the address book. note ? the flag bits are d efined as: b7 b6 b5 b4 b3 b2 b1 b0 rsvd rsvd filter lock new old age valid where filter ? 1 indicates the frame heading to this address should be dropped. lock ? 1 indicates the entry should never be changed or aged out. new ? 1 indicates the entry is a newly learned address. old ? 1 indicates the address has been aged out. age ? 1 indicates the address has not been visited for current age cycle. valid ? 1 indicates the entry is a valid one. rsvd ? reserved bits. command 11h description: read next entry of address book. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of the address book entry pointed by read pointer will be stored into the data registers. the mac addre ss will be stored into datareg5 ? datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer will be increased by one. comman d 20h description: read first valid entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of first valid entry of the address book will be stored into the data registers. th e mac address will be stored into datareg5 ? datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to thi s entry. command 21h description: read next valid entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of next valid entry from the read pointer of the address book will b e stored into the data registers. the mac address will be stored into datareg5 ? datareg0, with datareg5
page 73 of 77 confidential page 73 73 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 30h description: read first new entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of first new entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 ? datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in d atareg7. the read pointer is set to point to this entry.
page 74 of 77 confidential page 74 74 command 31h description: read next new entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of next new entry fro m the read pointer of the address book will be stored into the data registers. the mac address will be stored into datareg5 ? datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 40h description: read first aged entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error , the content of first aged entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 ? datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is store d in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 41h description: read next aged entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of next aged entry from the read pointer of the address book will be stored into the data registers. the mac address will be stored into datareg5 ? datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 50h description: read first locked entry. parameter: none result: the result is indicated by the result r egister. if the command is completed with no error, the content of first locked entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 ? datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry.
page 75 of 77 confidential page 75 75 command 51h description: read next locked entry. parameter: none result: the result is indicat ed by the result register. if the command is completed with no error, the content of next locked entry from the read pointer of the address book will be stored into the data registers. the mac address will be stored into datareg5 ? datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 60h description: read first filtered entry. param eter: none result: the result is indicated by the result register. if the command is completed with no error, the content of first filtered entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 ? da tareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 61h description: read next v alid entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of next filtered entry from the read pointer of the address book will be stored into the data registers. the mac ad dress will be stored into datareg5 ? datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 80h description: read first entry with specified port number. parameter: store port number into datareg6. result: the result is indicated by the result register. if the command is completed with no error, the content of first entry of the addr ess book with the said port number will be stored into the data registers. the mac address will be stored into datareg5 ? datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry.
page 76 of 77 confidential page 76 76 command 81h description: read next valid entry. parameter: store port number into datareg6. result: the result is indicated by the result register. if the command is completed with no error, the content of next entry from the read pointer of the address book with the said port number will be stored into the data registers. the mac address will be stored into datareg5 ? datareg0, with datareg5 contains the msb of the m ac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command ffh description: arl reset. parameter: none result: this command will res et the arl. all entries of the address book will be cleared and set the bit - 0 of register - 20 to one to wake up arl engine

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